163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 263944891SThierry Reding /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 663944891SThierry Reding 7fc5e0e37SMikko Perttunen /** 8fc5e0e37SMikko Perttunen * @file 9fc5e0e37SMikko Perttunen * @defgroup bpmp_clock_ids Clock ID's 10fc5e0e37SMikko Perttunen * @{ 11fc5e0e37SMikko Perttunen */ 12c3859c14SThierry Reding /** 13c3859c14SThierry Reding * @brief controls the EMC clock frequency. 14c3859c14SThierry Reding * @details Doing a clk_set_rate on this clock will select the 15c3859c14SThierry Reding * appropriate clock source, program the source rate and execute a 16c3859c14SThierry Reding * specific sequence to switch to the new clock source for both memory 17c3859c14SThierry Reding * controllers. This can be used to control the balance between memory 18c3859c14SThierry Reding * throughput and memory controller power. 19c3859c14SThierry Reding */ 20c3859c14SThierry Reding #define TEGRA234_CLK_EMC 31U 2163944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */ 22fc5e0e37SMikko Perttunen #define TEGRA234_CLK_FUSE 40U 23*bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ 24*bb747becSAkhil R #define TEGRA234_CLK_I2C1 48U 25*bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 26*bb747becSAkhil R #define TEGRA234_CLK_I2C2 49U 27*bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 28*bb747becSAkhil R #define TEGRA234_CLK_I2C3 50U 29*bb747becSAkhil R /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 30*bb747becSAkhil R #define TEGRA234_CLK_I2C4 51U 31*bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 32*bb747becSAkhil R #define TEGRA234_CLK_I2C6 52U 33*bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 34*bb747becSAkhil R #define TEGRA234_CLK_I2C7 53U 35*bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 36*bb747becSAkhil R #define TEGRA234_CLK_I2C8 54U 37*bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 38*bb747becSAkhil R #define TEGRA234_CLK_I2C9 55U 39*bb747becSAkhil R /** @brief PLLP clk output */ 40*bb747becSAkhil R #define TEGRA234_CLK_PLLP_OUT0 102U 4163944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 42fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC4 123U 4363944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 44fc5e0e37SMikko Perttunen #define TEGRA234_CLK_UARTA 155U 45fc5e0e37SMikko Perttunen /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 46fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 47fc5e0e37SMikko Perttunen /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 48fc5e0e37SMikko Perttunen #define TEGRA234_CLK_PLLC4 237U 49fc5e0e37SMikko Perttunen /** @brief 32K input clock provided by PMIC */ 50fc5e0e37SMikko Perttunen #define TEGRA234_CLK_CLK_32K 289U 5163944891SThierry Reding #endif 52