163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 240efe139SSameer Pujar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 663944891SThierry Reding 7fc5e0e37SMikko Perttunen /** 8fc5e0e37SMikko Perttunen * @file 9fc5e0e37SMikko Perttunen * @defgroup bpmp_clock_ids Clock ID's 10fc5e0e37SMikko Perttunen * @{ 11fc5e0e37SMikko Perttunen */ 1240efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 1340efe139SSameer Pujar #define TEGRA234_CLK_AHUB 4U 1440efe139SSameer Pujar /** @brief output of gate CLK_ENB_APB2APE */ 1540efe139SSameer Pujar #define TEGRA234_CLK_APB2APE 5U 1640efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 1740efe139SSameer Pujar #define TEGRA234_CLK_APE 6U 1840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 1940efe139SSameer Pujar #define TEGRA234_CLK_AUD_MCLK 7U 2040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 2140efe139SSameer Pujar #define TEGRA234_CLK_DMIC1 15U 2240efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 2340efe139SSameer Pujar #define TEGRA234_CLK_DMIC2 16U 2440efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 2540efe139SSameer Pujar #define TEGRA234_CLK_DMIC3 17U 2640efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 2740efe139SSameer Pujar #define TEGRA234_CLK_DMIC4 18U 2840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 2940efe139SSameer Pujar #define TEGRA234_CLK_DSPK1 29U 3040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 3140efe139SSameer Pujar #define TEGRA234_CLK_DSPK2 30U 32c3859c14SThierry Reding /** 33c3859c14SThierry Reding * @brief controls the EMC clock frequency. 34c3859c14SThierry Reding * @details Doing a clk_set_rate on this clock will select the 35c3859c14SThierry Reding * appropriate clock source, program the source rate and execute a 36c3859c14SThierry Reding * specific sequence to switch to the new clock source for both memory 37c3859c14SThierry Reding * controllers. This can be used to control the balance between memory 38c3859c14SThierry Reding * throughput and memory controller power. 39c3859c14SThierry Reding */ 40c3859c14SThierry Reding #define TEGRA234_CLK_EMC 31U 4163944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */ 42fc5e0e37SMikko Perttunen #define TEGRA234_CLK_FUSE 40U 43bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ 44bb747becSAkhil R #define TEGRA234_CLK_I2C1 48U 45bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 46bb747becSAkhil R #define TEGRA234_CLK_I2C2 49U 47bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 48bb747becSAkhil R #define TEGRA234_CLK_I2C3 50U 49bb747becSAkhil R /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 50bb747becSAkhil R #define TEGRA234_CLK_I2C4 51U 51bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 52bb747becSAkhil R #define TEGRA234_CLK_I2C6 52U 53bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 54bb747becSAkhil R #define TEGRA234_CLK_I2C7 53U 55bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 56bb747becSAkhil R #define TEGRA234_CLK_I2C8 54U 57bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 58bb747becSAkhil R #define TEGRA234_CLK_I2C9 55U 5940efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 6040efe139SSameer Pujar #define TEGRA234_CLK_I2S1 56U 6140efe139SSameer Pujar /** @brief clock recovered from I2S1 input */ 6240efe139SSameer Pujar #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U 6340efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 6440efe139SSameer Pujar #define TEGRA234_CLK_I2S2 58U 6540efe139SSameer Pujar /** @brief clock recovered from I2S2 input */ 6640efe139SSameer Pujar #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U 6740efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 6840efe139SSameer Pujar #define TEGRA234_CLK_I2S3 60U 6940efe139SSameer Pujar /** @brief clock recovered from I2S3 input */ 7040efe139SSameer Pujar #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U 7140efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 7240efe139SSameer Pujar #define TEGRA234_CLK_I2S4 62U 7340efe139SSameer Pujar /** @brief clock recovered from I2S4 input */ 7440efe139SSameer Pujar #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U 7540efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 7640efe139SSameer Pujar #define TEGRA234_CLK_I2S5 64U 7740efe139SSameer Pujar /** @brief clock recovered from I2S5 input */ 7840efe139SSameer Pujar #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U 7940efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ 8040efe139SSameer Pujar #define TEGRA234_CLK_I2S6 66U 8140efe139SSameer Pujar /** @brief clock recovered from I2S6 input */ 8240efe139SSameer Pujar #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U 8340efe139SSameer Pujar /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 8440efe139SSameer Pujar #define TEGRA234_CLK_PLLA 93U 85bb747becSAkhil R /** @brief PLLP clk output */ 86bb747becSAkhil R #define TEGRA234_CLK_PLLP_OUT0 102U 8740efe139SSameer Pujar /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 8840efe139SSameer Pujar #define TEGRA234_CLK_PLLA_OUT0 104U 8938eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 9038eb21a5SAkhil R #define TEGRA234_CLK_PWM1 105U 9138eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 9238eb21a5SAkhil R #define TEGRA234_CLK_PWM2 106U 9338eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 9438eb21a5SAkhil R #define TEGRA234_CLK_PWM3 107U 9538eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 9638eb21a5SAkhil R #define TEGRA234_CLK_PWM4 108U 9738eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 9838eb21a5SAkhil R #define TEGRA234_CLK_PWM5 109U 9938eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 10038eb21a5SAkhil R #define TEGRA234_CLK_PWM6 110U 10138eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 10238eb21a5SAkhil R #define TEGRA234_CLK_PWM7 111U 10338eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 10438eb21a5SAkhil R #define TEGRA234_CLK_PWM8 112U 10563944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 106fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC4 123U 10740efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 10840efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC1 139U 10940efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 11040efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC2 140U 11140efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 11240efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC3 141U 11340efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 11440efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC4 142U 11540efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 11640efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DSPK1 143U 11740efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 11840efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DSPK2 144U 11940efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 12040efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S1 145U 12140efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 12240efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S2 146U 12340efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 12440efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S3 147U 12540efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 12640efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S4 148U 12740efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 12840efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S5 149U 12940efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 13040efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S6 150U 13163944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 132fc5e0e37SMikko Perttunen #define TEGRA234_CLK_UARTA 155U 133d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ 134d06a171eSVidya Sagar #define TEGRA234_CLK_PEX1_C6_CORE 161U 135d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ 136d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C7_CORE 171U 137d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ 138d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C8_CORE 172U 139d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ 140d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C9_CORE 173U 141d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ 142d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C10_CORE 187U 14371f69ffaSAshish Singhal /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ 14471f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI0_2X_PM 192U 14571f69ffaSAshish Singhal /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ 14671f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI1_2X_PM 193U 14771f69ffaSAshish Singhal /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ 14871f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI0_PM 194U 14971f69ffaSAshish Singhal /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ 15071f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI1_PM 195U 151fc5e0e37SMikko Perttunen /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 152fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 153d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ 154d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C0_CORE 220U 155d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_1 */ 156d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C1_CORE 221U 157d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_2 */ 158d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C2_CORE 222U 159d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_3 */ 160d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C3_CORE 223U 161d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_4 */ 162d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C4_CORE 224U 163d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ 164d06a171eSVidya Sagar #define TEGRA234_CLK_PEX1_C5_CORE 225U 165fc5e0e37SMikko Perttunen /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 166fc5e0e37SMikko Perttunen #define TEGRA234_CLK_PLLC4 237U 167*b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE0 lane input */ 168*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_INPUT 248U 169*b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE1 lane input */ 170*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_INPUT 249U 171*b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE2 lane input */ 172*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_INPUT 250U 173*b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE3 lane input */ 174*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_INPUT 251U 175fc5e0e37SMikko Perttunen /** @brief 32K input clock provided by PMIC */ 176fc5e0e37SMikko Perttunen #define TEGRA234_CLK_CLK_32K 289U 177*b0aedf34SThierry Reding /** @brief Monitored branch of MBGE0 RX input clock */ 178*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U 179*b0aedf34SThierry Reding /** @brief Monitored branch of MBGE1 RX input clock */ 180*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U 181*b0aedf34SThierry Reding /** @brief Monitored branch of MBGE2 RX input clock */ 182*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U 183*b0aedf34SThierry Reding /** @brief Monitored branch of MBGE3 RX input clock */ 184*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U 185*b0aedf34SThierry Reding /** @brief Monitored branch of MGBE0 RX PCS mux output */ 186*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS_M 361U 187*b0aedf34SThierry Reding /** @brief Monitored branch of MGBE1 RX PCS mux output */ 188*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS_M 362U 189*b0aedf34SThierry Reding /** @brief Monitored branch of MGBE2 RX PCS mux output */ 190*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U 191*b0aedf34SThierry Reding /** @brief Monitored branch of MGBE3 RX PCS mux output */ 192*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U 193*b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE0 lane input */ 194*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U 195*b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE1 lane input */ 196*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U 197*b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE2 lane input */ 198*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U 199*b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE3 lane input */ 200*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U 201*b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ 202*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS 373U 203*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ 204*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_TX 374U 205*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ 206*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_TX_PCS 375U 207*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ 208*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U 209*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ 210*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MAC 377U 211*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ 212*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MACSEC 378U 213*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ 214*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_EEE_PCS 379U 215*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ 216*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_APP 380U 217*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ 218*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_PTP_REF 381U 219*b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ 220*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS 382U 221*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ 222*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_TX 383U 223*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ 224*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_TX_PCS 384U 225*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ 226*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U 227*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ 228*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_MAC 386U 229*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ 230*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_EEE_PCS 388U 231*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ 232*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_APP 389U 233*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ 234*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_PTP_REF 390U 235*b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ 236*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS 391U 237*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ 238*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_TX 392U 239*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ 240*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_TX_PCS 393U 241*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ 242*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U 243*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ 244*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_MAC 395U 245*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ 246*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_EEE_PCS 397U 247*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ 248*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_APP 398U 249*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ 250*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_PTP_REF 399U 251*b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ 252*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS 400U 253*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ 254*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_TX 401U 255*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ 256*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_TX_PCS 402U 257*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ 258*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U 259*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ 260*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MAC 404U 261*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ 262*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MACSEC 405U 263*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ 264*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_EEE_PCS 406U 265*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ 266*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_APP 407U 267*b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ 268*b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_PTP_REF 408U 26907d74390SMohan Kumar /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ 27007d74390SMohan Kumar #define TEGRA234_CLK_AZA_2XBIT 457U 27107d74390SMohan Kumar /** @brief aza_2xbitclk / 2 (aza_bitclk) */ 27207d74390SMohan Kumar #define TEGRA234_CLK_AZA_BIT 458U 273*b0aedf34SThierry Reding 27463944891SThierry Reding #endif 275