163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 263944891SThierry Reding /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 663944891SThierry Reding 763944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */ 863944891SThierry Reding #define TEGRA234_CLK_FUSE 40 963944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 1063944891SThierry Reding #define TEGRA234_CLK_SDMMC4 123 1163944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 1263944891SThierry Reding #define TEGRA234_CLK_UARTA 155 1363944891SThierry Reding 1463944891SThierry Reding #endif 15