163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 2*40efe139SSameer Pujar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 663944891SThierry Reding 7fc5e0e37SMikko Perttunen /** 8fc5e0e37SMikko Perttunen * @file 9fc5e0e37SMikko Perttunen * @defgroup bpmp_clock_ids Clock ID's 10fc5e0e37SMikko Perttunen * @{ 11fc5e0e37SMikko Perttunen */ 12*40efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 13*40efe139SSameer Pujar #define TEGRA234_CLK_AHUB 4U 14*40efe139SSameer Pujar /** @brief output of gate CLK_ENB_APB2APE */ 15*40efe139SSameer Pujar #define TEGRA234_CLK_APB2APE 5U 16*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 17*40efe139SSameer Pujar #define TEGRA234_CLK_APE 6U 18*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 19*40efe139SSameer Pujar #define TEGRA234_CLK_AUD_MCLK 7U 20*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 21*40efe139SSameer Pujar #define TEGRA234_CLK_DMIC1 15U 22*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 23*40efe139SSameer Pujar #define TEGRA234_CLK_DMIC2 16U 24*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 25*40efe139SSameer Pujar #define TEGRA234_CLK_DMIC3 17U 26*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 27*40efe139SSameer Pujar #define TEGRA234_CLK_DMIC4 18U 28*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 29*40efe139SSameer Pujar #define TEGRA234_CLK_DSPK1 29U 30*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 31*40efe139SSameer Pujar #define TEGRA234_CLK_DSPK2 30U 32c3859c14SThierry Reding /** 33c3859c14SThierry Reding * @brief controls the EMC clock frequency. 34c3859c14SThierry Reding * @details Doing a clk_set_rate on this clock will select the 35c3859c14SThierry Reding * appropriate clock source, program the source rate and execute a 36c3859c14SThierry Reding * specific sequence to switch to the new clock source for both memory 37c3859c14SThierry Reding * controllers. This can be used to control the balance between memory 38c3859c14SThierry Reding * throughput and memory controller power. 39c3859c14SThierry Reding */ 40c3859c14SThierry Reding #define TEGRA234_CLK_EMC 31U 4163944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */ 42fc5e0e37SMikko Perttunen #define TEGRA234_CLK_FUSE 40U 43bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ 44bb747becSAkhil R #define TEGRA234_CLK_I2C1 48U 45bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 46bb747becSAkhil R #define TEGRA234_CLK_I2C2 49U 47bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 48bb747becSAkhil R #define TEGRA234_CLK_I2C3 50U 49bb747becSAkhil R /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 50bb747becSAkhil R #define TEGRA234_CLK_I2C4 51U 51bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 52bb747becSAkhil R #define TEGRA234_CLK_I2C6 52U 53bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 54bb747becSAkhil R #define TEGRA234_CLK_I2C7 53U 55bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 56bb747becSAkhil R #define TEGRA234_CLK_I2C8 54U 57bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 58bb747becSAkhil R #define TEGRA234_CLK_I2C9 55U 59*40efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 60*40efe139SSameer Pujar #define TEGRA234_CLK_I2S1 56U 61*40efe139SSameer Pujar /** @brief clock recovered from I2S1 input */ 62*40efe139SSameer Pujar #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U 63*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 64*40efe139SSameer Pujar #define TEGRA234_CLK_I2S2 58U 65*40efe139SSameer Pujar /** @brief clock recovered from I2S2 input */ 66*40efe139SSameer Pujar #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U 67*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 68*40efe139SSameer Pujar #define TEGRA234_CLK_I2S3 60U 69*40efe139SSameer Pujar /** @brief clock recovered from I2S3 input */ 70*40efe139SSameer Pujar #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U 71*40efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 72*40efe139SSameer Pujar #define TEGRA234_CLK_I2S4 62U 73*40efe139SSameer Pujar /** @brief clock recovered from I2S4 input */ 74*40efe139SSameer Pujar #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U 75*40efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 76*40efe139SSameer Pujar #define TEGRA234_CLK_I2S5 64U 77*40efe139SSameer Pujar /** @brief clock recovered from I2S5 input */ 78*40efe139SSameer Pujar #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U 79*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ 80*40efe139SSameer Pujar #define TEGRA234_CLK_I2S6 66U 81*40efe139SSameer Pujar /** @brief clock recovered from I2S6 input */ 82*40efe139SSameer Pujar #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U 83*40efe139SSameer Pujar /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 84*40efe139SSameer Pujar #define TEGRA234_CLK_PLLA 93U 85bb747becSAkhil R /** @brief PLLP clk output */ 86bb747becSAkhil R #define TEGRA234_CLK_PLLP_OUT0 102U 87*40efe139SSameer Pujar /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 88*40efe139SSameer Pujar #define TEGRA234_CLK_PLLA_OUT0 104U 8938eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 9038eb21a5SAkhil R #define TEGRA234_CLK_PWM1 105U 9138eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 9238eb21a5SAkhil R #define TEGRA234_CLK_PWM2 106U 9338eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 9438eb21a5SAkhil R #define TEGRA234_CLK_PWM3 107U 9538eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 9638eb21a5SAkhil R #define TEGRA234_CLK_PWM4 108U 9738eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 9838eb21a5SAkhil R #define TEGRA234_CLK_PWM5 109U 9938eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 10038eb21a5SAkhil R #define TEGRA234_CLK_PWM6 110U 10138eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 10238eb21a5SAkhil R #define TEGRA234_CLK_PWM7 111U 10338eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 10438eb21a5SAkhil R #define TEGRA234_CLK_PWM8 112U 10563944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 106fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC4 123U 107*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 108*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC1 139U 109*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 110*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC2 140U 111*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 112*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC3 141U 113*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 114*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC4 142U 115*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 116*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DSPK1 143U 117*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 118*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DSPK2 144U 119*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 120*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S1 145U 121*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 122*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S2 146U 123*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 124*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S3 147U 125*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 126*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S4 148U 127*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 128*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S5 149U 129*40efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 130*40efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S6 150U 13163944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 132fc5e0e37SMikko Perttunen #define TEGRA234_CLK_UARTA 155U 133fc5e0e37SMikko Perttunen /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 134fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 135fc5e0e37SMikko Perttunen /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 136fc5e0e37SMikko Perttunen #define TEGRA234_CLK_PLLC4 237U 137fc5e0e37SMikko Perttunen /** @brief 32K input clock provided by PMIC */ 138fc5e0e37SMikko Perttunen #define TEGRA234_CLK_CLK_32K 289U 13963944891SThierry Reding #endif 140