163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */
263944891SThierry Reding /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
363944891SThierry Reding 
463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
663944891SThierry Reding 
7fc5e0e37SMikko Perttunen /**
8fc5e0e37SMikko Perttunen  * @file
9fc5e0e37SMikko Perttunen  * @defgroup bpmp_clock_ids Clock ID's
10fc5e0e37SMikko Perttunen  * @{
11fc5e0e37SMikko Perttunen  */
12c3859c14SThierry Reding /**
13c3859c14SThierry Reding  * @brief controls the EMC clock frequency.
14c3859c14SThierry Reding  * @details Doing a clk_set_rate on this clock will select the
15c3859c14SThierry Reding  * appropriate clock source, program the source rate and execute a
16c3859c14SThierry Reding  * specific sequence to switch to the new clock source for both memory
17c3859c14SThierry Reding  * controllers. This can be used to control the balance between memory
18c3859c14SThierry Reding  * throughput and memory controller power.
19c3859c14SThierry Reding  */
20c3859c14SThierry Reding #define TEGRA234_CLK_EMC			31U
2163944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */
22fc5e0e37SMikko Perttunen #define TEGRA234_CLK_FUSE			40U
23bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
24bb747becSAkhil R #define TEGRA234_CLK_I2C1			48U
25bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
26bb747becSAkhil R #define TEGRA234_CLK_I2C2			49U
27bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
28bb747becSAkhil R #define TEGRA234_CLK_I2C3			50U
29bb747becSAkhil R /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
30bb747becSAkhil R #define TEGRA234_CLK_I2C4			51U
31bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
32bb747becSAkhil R #define TEGRA234_CLK_I2C6			52U
33bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
34bb747becSAkhil R #define TEGRA234_CLK_I2C7			53U
35bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
36bb747becSAkhil R #define TEGRA234_CLK_I2C8			54U
37bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
38bb747becSAkhil R #define TEGRA234_CLK_I2C9			55U
39bb747becSAkhil R /** @brief PLLP clk output */
40bb747becSAkhil R #define TEGRA234_CLK_PLLP_OUT0			102U
41*38eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
42*38eb21a5SAkhil R #define TEGRA234_CLK_PWM1			105U
43*38eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
44*38eb21a5SAkhil R #define TEGRA234_CLK_PWM2			106U
45*38eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
46*38eb21a5SAkhil R #define TEGRA234_CLK_PWM3			107U
47*38eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
48*38eb21a5SAkhil R #define TEGRA234_CLK_PWM4			108U
49*38eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
50*38eb21a5SAkhil R #define TEGRA234_CLK_PWM5			109U
51*38eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
52*38eb21a5SAkhil R #define TEGRA234_CLK_PWM6			110U
53*38eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
54*38eb21a5SAkhil R #define TEGRA234_CLK_PWM7			111U
55*38eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
56*38eb21a5SAkhil R #define TEGRA234_CLK_PWM8			112U
5763944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
58fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC4			123U
5963944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
60fc5e0e37SMikko Perttunen #define TEGRA234_CLK_UARTA			155U
61fc5e0e37SMikko Perttunen /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
62fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC_LEGACY_TM		219U
63fc5e0e37SMikko Perttunen /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
64fc5e0e37SMikko Perttunen #define TEGRA234_CLK_PLLC4			237U
65fc5e0e37SMikko Perttunen /** @brief 32K input clock provided by PMIC */
66fc5e0e37SMikko Perttunen #define TEGRA234_CLK_CLK_32K			289U
6763944891SThierry Reding #endif
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