163944891SThierry Reding /* SPDX-License-Identifier: GPL-2.0 */ 240efe139SSameer Pujar /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */ 363944891SThierry Reding 463944891SThierry Reding #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 563944891SThierry Reding #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 663944891SThierry Reding 7fc5e0e37SMikko Perttunen /** 8fc5e0e37SMikko Perttunen * @file 9fc5e0e37SMikko Perttunen * @defgroup bpmp_clock_ids Clock ID's 10fc5e0e37SMikko Perttunen * @{ 11fc5e0e37SMikko Perttunen */ 1240efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ 1340efe139SSameer Pujar #define TEGRA234_CLK_AHUB 4U 1440efe139SSameer Pujar /** @brief output of gate CLK_ENB_APB2APE */ 1540efe139SSameer Pujar #define TEGRA234_CLK_APB2APE 5U 1640efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ 1740efe139SSameer Pujar #define TEGRA234_CLK_APE 6U 1840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ 1940efe139SSameer Pujar #define TEGRA234_CLK_AUD_MCLK 7U 2040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ 2140efe139SSameer Pujar #define TEGRA234_CLK_DMIC1 15U 2240efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ 2340efe139SSameer Pujar #define TEGRA234_CLK_DMIC2 16U 2440efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ 2540efe139SSameer Pujar #define TEGRA234_CLK_DMIC3 17U 2640efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ 2740efe139SSameer Pujar #define TEGRA234_CLK_DMIC4 18U 2840efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ 2940efe139SSameer Pujar #define TEGRA234_CLK_DSPK1 29U 3040efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ 3140efe139SSameer Pujar #define TEGRA234_CLK_DSPK2 30U 32c3859c14SThierry Reding /** 33c3859c14SThierry Reding * @brief controls the EMC clock frequency. 34c3859c14SThierry Reding * @details Doing a clk_set_rate on this clock will select the 35c3859c14SThierry Reding * appropriate clock source, program the source rate and execute a 36c3859c14SThierry Reding * specific sequence to switch to the new clock source for both memory 37c3859c14SThierry Reding * controllers. This can be used to control the balance between memory 38c3859c14SThierry Reding * throughput and memory controller power. 39c3859c14SThierry Reding */ 40c3859c14SThierry Reding #define TEGRA234_CLK_EMC 31U 4163a6ef23SMikko Perttunen /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ 4263a6ef23SMikko Perttunen #define TEGRA234_CLK_HOST1X 46U 4363944891SThierry Reding /** @brief output of gate CLK_ENB_FUSE */ 44fc5e0e37SMikko Perttunen #define TEGRA234_CLK_FUSE 40U 45bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ 46bb747becSAkhil R #define TEGRA234_CLK_I2C1 48U 47bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ 48bb747becSAkhil R #define TEGRA234_CLK_I2C2 49U 49bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ 50bb747becSAkhil R #define TEGRA234_CLK_I2C3 50U 51bb747becSAkhil R /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ 52bb747becSAkhil R #define TEGRA234_CLK_I2C4 51U 53bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ 54bb747becSAkhil R #define TEGRA234_CLK_I2C6 52U 55bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ 56bb747becSAkhil R #define TEGRA234_CLK_I2C7 53U 57bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ 58bb747becSAkhil R #define TEGRA234_CLK_I2C8 54U 59bb747becSAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ 60bb747becSAkhil R #define TEGRA234_CLK_I2C9 55U 6140efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ 6240efe139SSameer Pujar #define TEGRA234_CLK_I2S1 56U 6340efe139SSameer Pujar /** @brief clock recovered from I2S1 input */ 6440efe139SSameer Pujar #define TEGRA234_CLK_I2S1_SYNC_INPUT 57U 6540efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ 6640efe139SSameer Pujar #define TEGRA234_CLK_I2S2 58U 6740efe139SSameer Pujar /** @brief clock recovered from I2S2 input */ 6840efe139SSameer Pujar #define TEGRA234_CLK_I2S2_SYNC_INPUT 59U 6940efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ 7040efe139SSameer Pujar #define TEGRA234_CLK_I2S3 60U 7140efe139SSameer Pujar /** @brief clock recovered from I2S3 input */ 7240efe139SSameer Pujar #define TEGRA234_CLK_I2S3_SYNC_INPUT 61U 7340efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ 7440efe139SSameer Pujar #define TEGRA234_CLK_I2S4 62U 7540efe139SSameer Pujar /** @brief clock recovered from I2S4 input */ 7640efe139SSameer Pujar #define TEGRA234_CLK_I2S4_SYNC_INPUT 63U 7740efe139SSameer Pujar /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ 7840efe139SSameer Pujar #define TEGRA234_CLK_I2S5 64U 7940efe139SSameer Pujar /** @brief clock recovered from I2S5 input */ 8040efe139SSameer Pujar #define TEGRA234_CLK_I2S5_SYNC_INPUT 65U 8140efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */ 8240efe139SSameer Pujar #define TEGRA234_CLK_I2S6 66U 8340efe139SSameer Pujar /** @brief clock recovered from I2S6 input */ 8440efe139SSameer Pujar #define TEGRA234_CLK_I2S6_SYNC_INPUT 67U 85*0e2b014eSMikko Perttunen /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ 86*0e2b014eSMikko Perttunen #define TEGRA234_CLK_NVDEC 83U 8740efe139SSameer Pujar /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ 8840efe139SSameer Pujar #define TEGRA234_CLK_PLLA 93U 89bb747becSAkhil R /** @brief PLLP clk output */ 90bb747becSAkhil R #define TEGRA234_CLK_PLLP_OUT0 102U 9140efe139SSameer Pujar /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ 9240efe139SSameer Pujar #define TEGRA234_CLK_PLLA_OUT0 104U 9338eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ 9438eb21a5SAkhil R #define TEGRA234_CLK_PWM1 105U 9538eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ 9638eb21a5SAkhil R #define TEGRA234_CLK_PWM2 106U 9738eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ 9838eb21a5SAkhil R #define TEGRA234_CLK_PWM3 107U 9938eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ 10038eb21a5SAkhil R #define TEGRA234_CLK_PWM4 108U 10138eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ 10238eb21a5SAkhil R #define TEGRA234_CLK_PWM5 109U 10338eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ 10438eb21a5SAkhil R #define TEGRA234_CLK_PWM6 110U 10538eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ 10638eb21a5SAkhil R #define TEGRA234_CLK_PWM7 111U 10738eb21a5SAkhil R /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ 10838eb21a5SAkhil R #define TEGRA234_CLK_PWM8 112U 10963944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 110fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC4 123U 11140efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ 11240efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC1 139U 11340efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ 11440efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC2 140U 11540efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ 11640efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC3 141U 11740efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ 11840efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DMIC4 142U 11940efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ 12040efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DSPK1 143U 12140efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ 12240efe139SSameer Pujar #define TEGRA234_CLK_SYNC_DSPK2 144U 12340efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ 12440efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S1 145U 12540efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ 12640efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S2 146U 12740efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ 12840efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S3 147U 12940efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ 13040efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S4 148U 13140efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ 13240efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S5 149U 13340efe139SSameer Pujar /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ 13440efe139SSameer Pujar #define TEGRA234_CLK_SYNC_I2S6 150U 135*0e2b014eSMikko Perttunen /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PKA */ 136*0e2b014eSMikko Perttunen #define TEGRA234_CLK_TSEC_PKA 154U 13763944891SThierry Reding /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 138fc5e0e37SMikko Perttunen #define TEGRA234_CLK_UARTA 155U 139d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ 140d06a171eSVidya Sagar #define TEGRA234_CLK_PEX1_C6_CORE 161U 14163a6ef23SMikko Perttunen /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ 14263a6ef23SMikko Perttunen #define TEGRA234_CLK_VIC 167U 143d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ 144d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C7_CORE 171U 145d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ 146d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C8_CORE 172U 147d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_9 */ 148d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C9_CORE 173U 149d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ 150d06a171eSVidya Sagar #define TEGRA234_CLK_PEX2_C10_CORE 187U 15171f69ffaSAshish Singhal /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ 15271f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI0_2X_PM 192U 15371f69ffaSAshish Singhal /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ 15471f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI1_2X_PM 193U 15571f69ffaSAshish Singhal /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ 15671f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI0_PM 194U 15771f69ffaSAshish Singhal /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ 15871f69ffaSAshish Singhal #define TEGRA234_CLK_QSPI1_PM 195U 159fc5e0e37SMikko Perttunen /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ 160fc5e0e37SMikko Perttunen #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U 161d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ 162d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C0_CORE 220U 163d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_1 */ 164d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C1_CORE 221U 165d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_2 */ 166d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C2_CORE 222U 167d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_3 */ 168d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C3_CORE 223U 169d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX0_CORE_4 */ 170d06a171eSVidya Sagar #define TEGRA234_CLK_PEX0_C4_CORE 224U 171d06a171eSVidya Sagar /** @brief output of gate CLK_ENB_PEX1_CORE_5 */ 172d06a171eSVidya Sagar #define TEGRA234_CLK_PEX1_C5_CORE 225U 173fc5e0e37SMikko Perttunen /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ 174fc5e0e37SMikko Perttunen #define TEGRA234_CLK_PLLC4 237U 175b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE0 lane input */ 176b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_INPUT 248U 177b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE1 lane input */ 178b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_INPUT 249U 179b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE2 lane input */ 180b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_INPUT 250U 181b0aedf34SThierry Reding /** @brief RX clock recovered from MGBE3 lane input */ 182b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_INPUT 251U 183fc5e0e37SMikko Perttunen /** @brief 32K input clock provided by PMIC */ 184fc5e0e37SMikko Perttunen #define TEGRA234_CLK_CLK_32K 289U 185b0aedf34SThierry Reding /** @brief Monitored branch of MBGE0 RX input clock */ 186b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_INPUT_M 357U 187b0aedf34SThierry Reding /** @brief Monitored branch of MBGE1 RX input clock */ 188b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_INPUT_M 358U 189b0aedf34SThierry Reding /** @brief Monitored branch of MBGE2 RX input clock */ 190b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_INPUT_M 359U 191b0aedf34SThierry Reding /** @brief Monitored branch of MBGE3 RX input clock */ 192b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_INPUT_M 360U 193b0aedf34SThierry Reding /** @brief Monitored branch of MGBE0 RX PCS mux output */ 194b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS_M 361U 195b0aedf34SThierry Reding /** @brief Monitored branch of MGBE1 RX PCS mux output */ 196b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS_M 362U 197b0aedf34SThierry Reding /** @brief Monitored branch of MGBE2 RX PCS mux output */ 198b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS_M 363U 199b0aedf34SThierry Reding /** @brief Monitored branch of MGBE3 RX PCS mux output */ 200b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS_M 364U 201b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE0 lane input */ 202b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS_INPUT 369U 203b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE1 lane input */ 204b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS_INPUT 370U 205b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE2 lane input */ 206b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS_INPUT 371U 207b0aedf34SThierry Reding /** @brief RX PCS clock recovered from MGBE3 lane input */ 208b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS_INPUT 372U 209b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE0_RX_PCS_CLK_SRC_SEL */ 210b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_RX_PCS 373U 211b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */ 212b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_TX 374U 213b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */ 214b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_TX_PCS 375U 215b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MAC_CLK divider output */ 216b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MAC_DIVIDER 376U 217b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MAC_CLK gate output */ 218b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MAC 377U 219b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_MACSEC_CLK gate output */ 220b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_MACSEC 378U 221b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_EEE_PCS_CLK gate output */ 222b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_EEE_PCS 379U 223b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_APP_CLK gate output */ 224b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_APP 380U 225b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */ 226b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE0_PTP_REF 381U 227b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE1_RX_PCS_CLK_SRC_SEL */ 228b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_RX_PCS 382U 229b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */ 230b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_TX 383U 231b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */ 232b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_TX_PCS 384U 233b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_MAC_CLK divider output */ 234b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_MAC_DIVIDER 385U 235b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_MAC_CLK gate output */ 236b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_MAC 386U 237b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_EEE_PCS_CLK gate output */ 238b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_EEE_PCS 388U 239b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_APP_CLK gate output */ 240b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_APP 389U 241b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */ 242b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE1_PTP_REF 390U 243b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE2_RX_PCS_CLK_SRC_SEL */ 244b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_RX_PCS 391U 245b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */ 246b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_TX 392U 247b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */ 248b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_TX_PCS 393U 249b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_MAC_CLK divider output */ 250b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_MAC_DIVIDER 394U 251b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_MAC_CLK gate output */ 252b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_MAC 395U 253b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_EEE_PCS_CLK gate output */ 254b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_EEE_PCS 397U 255b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_APP_CLK gate output */ 256b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_APP 398U 257b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */ 258b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE2_PTP_REF 399U 259b0aedf34SThierry Reding /** @brief output of mux controlled by GBE_UPHY_MGBE3_RX_PCS_CLK_SRC_SEL */ 260b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_RX_PCS 400U 261b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */ 262b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_TX 401U 263b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */ 264b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_TX_PCS 402U 265b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MAC_CLK divider output */ 266b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MAC_DIVIDER 403U 267b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MAC_CLK gate output */ 268b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MAC 404U 269b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_MACSEC_CLK gate output */ 270b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_MACSEC 405U 271b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_EEE_PCS_CLK gate output */ 272b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_EEE_PCS 406U 273b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_APP_CLK gate output */ 274b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_APP 407U 275b0aedf34SThierry Reding /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */ 276b0aedf34SThierry Reding #define TEGRA234_CLK_MGBE3_PTP_REF 408U 27707d74390SMohan Kumar /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */ 27807d74390SMohan Kumar #define TEGRA234_CLK_AZA_2XBIT 457U 27907d74390SMohan Kumar /** @brief aza_2xbitclk / 2 (aza_bitclk) */ 28007d74390SMohan Kumar #define TEGRA234_CLK_AZA_BIT 458U 281b0aedf34SThierry Reding 28263944891SThierry Reding #endif 283