13fdd5972SPaul Walmsley /* 23fdd5972SPaul Walmsley * This header provides constants for binding nvidia,tegra124-car or 33fdd5972SPaul Walmsley * nvidia,tegra132-car. 43fdd5972SPaul Walmsley * 53fdd5972SPaul Walmsley * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 63fdd5972SPaul Walmsley * registers. These IDs often match those in the CAR's RST_DEVICES registers, 73fdd5972SPaul Walmsley * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 83fdd5972SPaul Walmsley * this case, those clocks are assigned IDs above 185 in order to highlight 93fdd5972SPaul Walmsley * this issue. Implementations that interpret these clock IDs as bit values 103fdd5972SPaul Walmsley * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 113fdd5972SPaul Walmsley * explicitly handle these special cases. 123fdd5972SPaul Walmsley * 133fdd5972SPaul Walmsley * The balance of the clocks controlled by the CAR are assigned IDs of 185 and 143fdd5972SPaul Walmsley * above. 153fdd5972SPaul Walmsley */ 163fdd5972SPaul Walmsley 173fdd5972SPaul Walmsley #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 183fdd5972SPaul Walmsley #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 193fdd5972SPaul Walmsley 203fdd5972SPaul Walmsley /* 0 */ 213fdd5972SPaul Walmsley /* 1 */ 223fdd5972SPaul Walmsley /* 2 */ 233fdd5972SPaul Walmsley #define TEGRA124_CLK_ISPB 3 243fdd5972SPaul Walmsley #define TEGRA124_CLK_RTC 4 253fdd5972SPaul Walmsley #define TEGRA124_CLK_TIMER 5 263fdd5972SPaul Walmsley #define TEGRA124_CLK_UARTA 6 273fdd5972SPaul Walmsley /* 7 (register bit affects uartb and vfir) */ 283fdd5972SPaul Walmsley /* 8 */ 293fdd5972SPaul Walmsley #define TEGRA124_CLK_SDMMC2 9 303fdd5972SPaul Walmsley /* 10 (register bit affects spdif_in and spdif_out) */ 313fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S1 11 323fdd5972SPaul Walmsley #define TEGRA124_CLK_I2C1 12 333fdd5972SPaul Walmsley /* 13 */ 343fdd5972SPaul Walmsley #define TEGRA124_CLK_SDMMC1 14 353fdd5972SPaul Walmsley #define TEGRA124_CLK_SDMMC4 15 363fdd5972SPaul Walmsley /* 16 */ 373fdd5972SPaul Walmsley #define TEGRA124_CLK_PWM 17 383fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S2 18 393fdd5972SPaul Walmsley /* 20 (register bit affects vi and vi_sensor) */ 403fdd5972SPaul Walmsley /* 21 */ 413fdd5972SPaul Walmsley #define TEGRA124_CLK_USBD 22 423fdd5972SPaul Walmsley #define TEGRA124_CLK_ISP 23 433fdd5972SPaul Walmsley /* 26 */ 443fdd5972SPaul Walmsley /* 25 */ 453fdd5972SPaul Walmsley #define TEGRA124_CLK_DISP2 26 463fdd5972SPaul Walmsley #define TEGRA124_CLK_DISP1 27 473fdd5972SPaul Walmsley #define TEGRA124_CLK_HOST1X 28 483fdd5972SPaul Walmsley #define TEGRA124_CLK_VCP 29 493fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S0 30 503fdd5972SPaul Walmsley /* 31 */ 513fdd5972SPaul Walmsley 523fdd5972SPaul Walmsley #define TEGRA124_CLK_MC 32 533fdd5972SPaul Walmsley /* 33 */ 543fdd5972SPaul Walmsley #define TEGRA124_CLK_APBDMA 34 553fdd5972SPaul Walmsley /* 35 */ 563fdd5972SPaul Walmsley #define TEGRA124_CLK_KBC 36 573fdd5972SPaul Walmsley /* 37 */ 583fdd5972SPaul Walmsley /* 38 */ 593fdd5972SPaul Walmsley /* 39 (register bit affects fuse and fuse_burn) */ 603fdd5972SPaul Walmsley #define TEGRA124_CLK_KFUSE 40 613fdd5972SPaul Walmsley #define TEGRA124_CLK_SBC1 41 623fdd5972SPaul Walmsley #define TEGRA124_CLK_NOR 42 633fdd5972SPaul Walmsley /* 43 */ 643fdd5972SPaul Walmsley #define TEGRA124_CLK_SBC2 44 653fdd5972SPaul Walmsley /* 45 */ 663fdd5972SPaul Walmsley #define TEGRA124_CLK_SBC3 46 673fdd5972SPaul Walmsley #define TEGRA124_CLK_I2C5 47 683fdd5972SPaul Walmsley #define TEGRA124_CLK_DSIA 48 693fdd5972SPaul Walmsley /* 49 */ 703fdd5972SPaul Walmsley #define TEGRA124_CLK_MIPI 50 713fdd5972SPaul Walmsley #define TEGRA124_CLK_HDMI 51 723fdd5972SPaul Walmsley #define TEGRA124_CLK_CSI 52 733fdd5972SPaul Walmsley /* 53 */ 743fdd5972SPaul Walmsley #define TEGRA124_CLK_I2C2 54 753fdd5972SPaul Walmsley #define TEGRA124_CLK_UARTC 55 763fdd5972SPaul Walmsley #define TEGRA124_CLK_MIPI_CAL 56 773fdd5972SPaul Walmsley #define TEGRA124_CLK_EMC 57 783fdd5972SPaul Walmsley #define TEGRA124_CLK_USB2 58 793fdd5972SPaul Walmsley #define TEGRA124_CLK_USB3 59 803fdd5972SPaul Walmsley /* 60 */ 813fdd5972SPaul Walmsley #define TEGRA124_CLK_VDE 61 823fdd5972SPaul Walmsley #define TEGRA124_CLK_BSEA 62 833fdd5972SPaul Walmsley #define TEGRA124_CLK_BSEV 63 843fdd5972SPaul Walmsley 853fdd5972SPaul Walmsley /* 64 */ 863fdd5972SPaul Walmsley #define TEGRA124_CLK_UARTD 65 873fdd5972SPaul Walmsley /* 66 */ 883fdd5972SPaul Walmsley #define TEGRA124_CLK_I2C3 67 893fdd5972SPaul Walmsley #define TEGRA124_CLK_SBC4 68 903fdd5972SPaul Walmsley #define TEGRA124_CLK_SDMMC3 69 913fdd5972SPaul Walmsley #define TEGRA124_CLK_PCIE 70 923fdd5972SPaul Walmsley #define TEGRA124_CLK_OWR 71 933fdd5972SPaul Walmsley #define TEGRA124_CLK_AFI 72 943fdd5972SPaul Walmsley #define TEGRA124_CLK_CSITE 73 953fdd5972SPaul Walmsley /* 74 */ 963fdd5972SPaul Walmsley /* 75 */ 973fdd5972SPaul Walmsley #define TEGRA124_CLK_LA 76 983fdd5972SPaul Walmsley #define TEGRA124_CLK_TRACE 77 993fdd5972SPaul Walmsley #define TEGRA124_CLK_SOC_THERM 78 1003fdd5972SPaul Walmsley #define TEGRA124_CLK_DTV 79 1013fdd5972SPaul Walmsley /* 80 */ 1023fdd5972SPaul Walmsley #define TEGRA124_CLK_I2CSLOW 81 1033fdd5972SPaul Walmsley #define TEGRA124_CLK_DSIB 82 1043fdd5972SPaul Walmsley #define TEGRA124_CLK_TSEC 83 1053fdd5972SPaul Walmsley /* 84 */ 1063fdd5972SPaul Walmsley /* 85 */ 1073fdd5972SPaul Walmsley /* 86 */ 1083fdd5972SPaul Walmsley /* 87 */ 1093fdd5972SPaul Walmsley /* 88 */ 1103fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_HOST 89 1113fdd5972SPaul Walmsley /* 90 */ 1123fdd5972SPaul Walmsley #define TEGRA124_CLK_MSENC 91 1133fdd5972SPaul Walmsley #define TEGRA124_CLK_CSUS 92 1143fdd5972SPaul Walmsley /* 93 */ 1153fdd5972SPaul Walmsley /* 94 */ 1163fdd5972SPaul Walmsley /* 95 (bit affects xusb_dev and xusb_dev_src) */ 1173fdd5972SPaul Walmsley 1183fdd5972SPaul Walmsley /* 96 */ 1193fdd5972SPaul Walmsley /* 97 */ 1203fdd5972SPaul Walmsley /* 98 */ 1213fdd5972SPaul Walmsley #define TEGRA124_CLK_MSELECT 99 1223fdd5972SPaul Walmsley #define TEGRA124_CLK_TSENSOR 100 1233fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S3 101 1243fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S4 102 1253fdd5972SPaul Walmsley #define TEGRA124_CLK_I2C4 103 1263fdd5972SPaul Walmsley #define TEGRA124_CLK_SBC5 104 1273fdd5972SPaul Walmsley #define TEGRA124_CLK_SBC6 105 1283fdd5972SPaul Walmsley #define TEGRA124_CLK_D_AUDIO 106 1293fdd5972SPaul Walmsley #define TEGRA124_CLK_APBIF 107 1303fdd5972SPaul Walmsley #define TEGRA124_CLK_DAM0 108 1313fdd5972SPaul Walmsley #define TEGRA124_CLK_DAM1 109 1323fdd5972SPaul Walmsley #define TEGRA124_CLK_DAM2 110 1333fdd5972SPaul Walmsley #define TEGRA124_CLK_HDA2CODEC_2X 111 1343fdd5972SPaul Walmsley /* 112 */ 1353fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO0_2X 113 1363fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO1_2X 114 1373fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO2_2X 115 1383fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO3_2X 116 1393fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO4_2X 117 1403fdd5972SPaul Walmsley #define TEGRA124_CLK_SPDIF_2X 118 1413fdd5972SPaul Walmsley #define TEGRA124_CLK_ACTMON 119 1423fdd5972SPaul Walmsley #define TEGRA124_CLK_EXTERN1 120 1433fdd5972SPaul Walmsley #define TEGRA124_CLK_EXTERN2 121 1443fdd5972SPaul Walmsley #define TEGRA124_CLK_EXTERN3 122 1453fdd5972SPaul Walmsley #define TEGRA124_CLK_SATA_OOB 123 1463fdd5972SPaul Walmsley #define TEGRA124_CLK_SATA 124 1473fdd5972SPaul Walmsley #define TEGRA124_CLK_HDA 125 1483fdd5972SPaul Walmsley /* 126 */ 1493fdd5972SPaul Walmsley #define TEGRA124_CLK_SE 127 1503fdd5972SPaul Walmsley 1513fdd5972SPaul Walmsley #define TEGRA124_CLK_HDA2HDMI 128 1523fdd5972SPaul Walmsley #define TEGRA124_CLK_SATA_COLD 129 1533fdd5972SPaul Walmsley /* 130 */ 1543fdd5972SPaul Walmsley /* 131 */ 1553fdd5972SPaul Walmsley /* 132 */ 1563fdd5972SPaul Walmsley /* 133 */ 1573fdd5972SPaul Walmsley /* 134 */ 1583fdd5972SPaul Walmsley /* 135 */ 1593fdd5972SPaul Walmsley /* 136 */ 1603fdd5972SPaul Walmsley /* 137 */ 1613fdd5972SPaul Walmsley /* 138 */ 1623fdd5972SPaul Walmsley /* 139 */ 1633fdd5972SPaul Walmsley /* 140 */ 1643fdd5972SPaul Walmsley /* 141 */ 1653fdd5972SPaul Walmsley /* 142 */ 1663fdd5972SPaul Walmsley /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 1673fdd5972SPaul Walmsley /* xusb_host_src and xusb_ss_src) */ 1683fdd5972SPaul Walmsley #define TEGRA124_CLK_CILAB 144 1693fdd5972SPaul Walmsley #define TEGRA124_CLK_CILCD 145 1703fdd5972SPaul Walmsley #define TEGRA124_CLK_CILE 146 1713fdd5972SPaul Walmsley #define TEGRA124_CLK_DSIALP 147 1723fdd5972SPaul Walmsley #define TEGRA124_CLK_DSIBLP 148 1733fdd5972SPaul Walmsley #define TEGRA124_CLK_ENTROPY 149 1743fdd5972SPaul Walmsley #define TEGRA124_CLK_DDS 150 1753fdd5972SPaul Walmsley /* 151 */ 1763fdd5972SPaul Walmsley #define TEGRA124_CLK_DP2 152 1773fdd5972SPaul Walmsley #define TEGRA124_CLK_AMX 153 1783fdd5972SPaul Walmsley #define TEGRA124_CLK_ADX 154 1793fdd5972SPaul Walmsley /* 155 (bit affects dfll_ref and dfll_soc) */ 1803fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_SS 156 1813fdd5972SPaul Walmsley /* 157 */ 1823fdd5972SPaul Walmsley /* 158 */ 1833fdd5972SPaul Walmsley /* 159 */ 1843fdd5972SPaul Walmsley 1853fdd5972SPaul Walmsley /* 160 */ 1863fdd5972SPaul Walmsley /* 161 */ 1873fdd5972SPaul Walmsley /* 162 */ 1883fdd5972SPaul Walmsley /* 163 */ 1893fdd5972SPaul Walmsley /* 164 */ 1903fdd5972SPaul Walmsley /* 165 */ 1913fdd5972SPaul Walmsley #define TEGRA124_CLK_I2C6 166 1923fdd5972SPaul Walmsley /* 167 */ 1933fdd5972SPaul Walmsley /* 168 */ 1943fdd5972SPaul Walmsley /* 169 */ 1953fdd5972SPaul Walmsley /* 170 */ 1963fdd5972SPaul Walmsley #define TEGRA124_CLK_VIM2_CLK 171 1973fdd5972SPaul Walmsley /* 172 */ 1983fdd5972SPaul Walmsley /* 173 */ 1993fdd5972SPaul Walmsley /* 174 */ 2003fdd5972SPaul Walmsley /* 175 */ 2013fdd5972SPaul Walmsley #define TEGRA124_CLK_HDMI_AUDIO 176 2023fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK72MHZ 177 2033fdd5972SPaul Walmsley #define TEGRA124_CLK_VIC03 178 2043fdd5972SPaul Walmsley /* 179 */ 2053fdd5972SPaul Walmsley #define TEGRA124_CLK_ADX1 180 2063fdd5972SPaul Walmsley #define TEGRA124_CLK_DPAUX 181 2073fdd5972SPaul Walmsley #define TEGRA124_CLK_SOR0 182 2083fdd5972SPaul Walmsley /* 183 */ 2093fdd5972SPaul Walmsley #define TEGRA124_CLK_GPU 184 2103fdd5972SPaul Walmsley #define TEGRA124_CLK_AMX1 185 2113fdd5972SPaul Walmsley /* 186 */ 2123fdd5972SPaul Walmsley /* 187 */ 2133fdd5972SPaul Walmsley /* 188 */ 2143fdd5972SPaul Walmsley /* 189 */ 2153fdd5972SPaul Walmsley /* 190 */ 2163fdd5972SPaul Walmsley /* 191 */ 2173fdd5972SPaul Walmsley #define TEGRA124_CLK_UARTB 192 2183fdd5972SPaul Walmsley #define TEGRA124_CLK_VFIR 193 2193fdd5972SPaul Walmsley #define TEGRA124_CLK_SPDIF_IN 194 2203fdd5972SPaul Walmsley #define TEGRA124_CLK_SPDIF_OUT 195 2213fdd5972SPaul Walmsley #define TEGRA124_CLK_VI 196 2223fdd5972SPaul Walmsley #define TEGRA124_CLK_VI_SENSOR 197 2233fdd5972SPaul Walmsley #define TEGRA124_CLK_FUSE 198 2243fdd5972SPaul Walmsley #define TEGRA124_CLK_FUSE_BURN 199 2253fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_32K 200 2263fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_M 201 2273fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_M_DIV2 202 2283fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_M_DIV4 203 2293fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_REF 204 2303fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_C 205 2313fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_C_OUT1 206 2323fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_C2 207 2333fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_C3 208 2343fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_M 209 2353fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_M_OUT1 210 2363fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_P 211 2373fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_P_OUT1 212 2383fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_P_OUT2 213 2393fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_P_OUT3 214 2403fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_P_OUT4 215 2413fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_A 216 2423fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_A_OUT0 217 2433fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_D 218 2443fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_D_OUT0 219 2453fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_D2 220 2463fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_D2_OUT0 221 2473fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_U 222 2483fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_U_480M 223 2493fdd5972SPaul Walmsley 2503fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_U_60M 224 2513fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_U_48M 225 2523fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_U_12M 226 2533fdd5972SPaul Walmsley /* 227 */ 2543fdd5972SPaul Walmsley /* 228 */ 2553fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_RE_VCO 229 2563fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_RE_OUT 230 2573fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_E 231 2583fdd5972SPaul Walmsley #define TEGRA124_CLK_SPDIF_IN_SYNC 232 2593fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S0_SYNC 233 2603fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S1_SYNC 234 2613fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S2_SYNC 235 2623fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S3_SYNC 236 2633fdd5972SPaul Walmsley #define TEGRA124_CLK_I2S4_SYNC 237 2643fdd5972SPaul Walmsley #define TEGRA124_CLK_VIMCLK_SYNC 238 2653fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO0 239 2663fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO1 240 2673fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO2 241 2683fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO3 242 2693fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO4 243 2703fdd5972SPaul Walmsley #define TEGRA124_CLK_SPDIF 244 2713fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_OUT_1 245 2723fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_OUT_2 246 2733fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_OUT_3 247 2743fdd5972SPaul Walmsley #define TEGRA124_CLK_BLINK 248 2753fdd5972SPaul Walmsley /* 249 */ 2763fdd5972SPaul Walmsley /* 250 */ 2773fdd5972SPaul Walmsley /* 251 */ 2783fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_HOST_SRC 252 2793fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_FALCON_SRC 253 2803fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_FS_SRC 254 2813fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_SS_SRC 255 2823fdd5972SPaul Walmsley 2833fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_DEV_SRC 256 2843fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_DEV 257 2853fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_HS_SRC 258 2863fdd5972SPaul Walmsley #define TEGRA124_CLK_SCLK 259 2873fdd5972SPaul Walmsley #define TEGRA124_CLK_HCLK 260 2883fdd5972SPaul Walmsley #define TEGRA124_CLK_PCLK 261 2893fdd5972SPaul Walmsley /* 262 */ 2903fdd5972SPaul Walmsley /* 263 */ 2913fdd5972SPaul Walmsley #define TEGRA124_CLK_DFLL_REF 264 2923fdd5972SPaul Walmsley #define TEGRA124_CLK_DFLL_SOC 265 2933fdd5972SPaul Walmsley #define TEGRA124_CLK_VI_SENSOR2 266 2943fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_P_OUT5 267 2953fdd5972SPaul Walmsley #define TEGRA124_CLK_CML0 268 2963fdd5972SPaul Walmsley #define TEGRA124_CLK_CML1 269 2973fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_C4 270 2983fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_DP 271 2993fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_E_MUX 272 300b270491eSMark Zhang #define TEGRA124_CLK_PLLD_DSI 273 3013fdd5972SPaul Walmsley /* 274 */ 3023fdd5972SPaul Walmsley /* 275 */ 3033fdd5972SPaul Walmsley /* 276 */ 3043fdd5972SPaul Walmsley /* 277 */ 3053fdd5972SPaul Walmsley /* 278 */ 3063fdd5972SPaul Walmsley /* 279 */ 3073fdd5972SPaul Walmsley /* 280 */ 3083fdd5972SPaul Walmsley /* 281 */ 3093fdd5972SPaul Walmsley /* 282 */ 3103fdd5972SPaul Walmsley /* 283 */ 3113fdd5972SPaul Walmsley /* 284 */ 3123fdd5972SPaul Walmsley /* 285 */ 3133fdd5972SPaul Walmsley /* 286 */ 3143fdd5972SPaul Walmsley /* 287 */ 3153fdd5972SPaul Walmsley 3163fdd5972SPaul Walmsley /* 288 */ 3173fdd5972SPaul Walmsley /* 289 */ 3183fdd5972SPaul Walmsley /* 290 */ 3193fdd5972SPaul Walmsley /* 291 */ 3203fdd5972SPaul Walmsley /* 292 */ 3213fdd5972SPaul Walmsley /* 293 */ 3223fdd5972SPaul Walmsley /* 294 */ 3233fdd5972SPaul Walmsley /* 295 */ 3243fdd5972SPaul Walmsley /* 296 */ 3253fdd5972SPaul Walmsley /* 297 */ 3263fdd5972SPaul Walmsley /* 298 */ 3273fdd5972SPaul Walmsley /* 299 */ 3283fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO0_MUX 300 3293fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO1_MUX 301 3303fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO2_MUX 302 3313fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO3_MUX 303 3323fdd5972SPaul Walmsley #define TEGRA124_CLK_AUDIO4_MUX 304 3333fdd5972SPaul Walmsley #define TEGRA124_CLK_SPDIF_MUX 305 3343fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_OUT_1_MUX 306 3353fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_OUT_2_MUX 307 3363fdd5972SPaul Walmsley #define TEGRA124_CLK_CLK_OUT_3_MUX 308 337b270491eSMark Zhang /* 309 */ 338b270491eSMark Zhang /* 310 */ 3393fdd5972SPaul Walmsley #define TEGRA124_CLK_SOR0_LVDS 311 3403fdd5972SPaul Walmsley #define TEGRA124_CLK_XUSB_SS_DIV2 312 3413fdd5972SPaul Walmsley 3423fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_M_UD 313 3433fdd5972SPaul Walmsley #define TEGRA124_CLK_PLL_C_UD 314 3443fdd5972SPaul Walmsley 3453fdd5972SPaul Walmsley #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ 346