1*5543604aSQin Jian /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*5543604aSQin Jian /* 3*5543604aSQin Jian * Copyright (C) Sunplus Technology Co., Ltd. 4*5543604aSQin Jian * All rights reserved. 5*5543604aSQin Jian */ 6*5543604aSQin Jian #ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H 7*5543604aSQin Jian #define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H 8*5543604aSQin Jian 9*5543604aSQin Jian /* gates */ 10*5543604aSQin Jian #define CLK_RTC 0 11*5543604aSQin Jian #define CLK_OTPRX 1 12*5543604aSQin Jian #define CLK_NOC 2 13*5543604aSQin Jian #define CLK_BR 3 14*5543604aSQin Jian #define CLK_SPIFL 4 15*5543604aSQin Jian #define CLK_PERI0 5 16*5543604aSQin Jian #define CLK_PERI1 6 17*5543604aSQin Jian #define CLK_STC0 7 18*5543604aSQin Jian #define CLK_STC_AV0 8 19*5543604aSQin Jian #define CLK_STC_AV1 9 20*5543604aSQin Jian #define CLK_STC_AV2 10 21*5543604aSQin Jian #define CLK_UA0 11 22*5543604aSQin Jian #define CLK_UA1 12 23*5543604aSQin Jian #define CLK_UA2 13 24*5543604aSQin Jian #define CLK_UA3 14 25*5543604aSQin Jian #define CLK_UA4 15 26*5543604aSQin Jian #define CLK_HWUA 16 27*5543604aSQin Jian #define CLK_DDC0 17 28*5543604aSQin Jian #define CLK_UADMA 18 29*5543604aSQin Jian #define CLK_CBDMA0 19 30*5543604aSQin Jian #define CLK_CBDMA1 20 31*5543604aSQin Jian #define CLK_SPI_COMBO_0 21 32*5543604aSQin Jian #define CLK_SPI_COMBO_1 22 33*5543604aSQin Jian #define CLK_SPI_COMBO_2 23 34*5543604aSQin Jian #define CLK_SPI_COMBO_3 24 35*5543604aSQin Jian #define CLK_AUD 25 36*5543604aSQin Jian #define CLK_USBC0 26 37*5543604aSQin Jian #define CLK_USBC1 27 38*5543604aSQin Jian #define CLK_UPHY0 28 39*5543604aSQin Jian #define CLK_UPHY1 29 40*5543604aSQin Jian #define CLK_I2CM0 30 41*5543604aSQin Jian #define CLK_I2CM1 31 42*5543604aSQin Jian #define CLK_I2CM2 32 43*5543604aSQin Jian #define CLK_I2CM3 33 44*5543604aSQin Jian #define CLK_PMC 34 45*5543604aSQin Jian #define CLK_CARD_CTL0 35 46*5543604aSQin Jian #define CLK_CARD_CTL1 36 47*5543604aSQin Jian #define CLK_CARD_CTL4 37 48*5543604aSQin Jian #define CLK_BCH 38 49*5543604aSQin Jian #define CLK_DDFCH 39 50*5543604aSQin Jian #define CLK_CSIIW0 40 51*5543604aSQin Jian #define CLK_CSIIW1 41 52*5543604aSQin Jian #define CLK_MIPICSI0 42 53*5543604aSQin Jian #define CLK_MIPICSI1 43 54*5543604aSQin Jian #define CLK_HDMI_TX 44 55*5543604aSQin Jian #define CLK_VPOST 45 56*5543604aSQin Jian #define CLK_TGEN 46 57*5543604aSQin Jian #define CLK_DMIX 47 58*5543604aSQin Jian #define CLK_TCON 48 59*5543604aSQin Jian #define CLK_GPIO 49 60*5543604aSQin Jian #define CLK_MAILBOX 50 61*5543604aSQin Jian #define CLK_SPIND 51 62*5543604aSQin Jian #define CLK_I2C2CBUS 52 63*5543604aSQin Jian #define CLK_SEC 53 64*5543604aSQin Jian #define CLK_DVE 54 65*5543604aSQin Jian #define CLK_GPOST0 55 66*5543604aSQin Jian #define CLK_OSD0 56 67*5543604aSQin Jian #define CLK_DISP_PWM 57 68*5543604aSQin Jian #define CLK_UADBG 58 69*5543604aSQin Jian #define CLK_FIO_CTL 59 70*5543604aSQin Jian #define CLK_FPGA 60 71*5543604aSQin Jian #define CLK_L2SW 61 72*5543604aSQin Jian #define CLK_ICM 62 73*5543604aSQin Jian #define CLK_AXI_GLOBAL 63 74*5543604aSQin Jian 75*5543604aSQin Jian /* plls */ 76*5543604aSQin Jian #define PLL_A 64 77*5543604aSQin Jian #define PLL_E 65 78*5543604aSQin Jian #define PLL_E_2P5 66 79*5543604aSQin Jian #define PLL_E_25 67 80*5543604aSQin Jian #define PLL_E_112P5 68 81*5543604aSQin Jian #define PLL_F 69 82*5543604aSQin Jian #define PLL_TV 70 83*5543604aSQin Jian #define PLL_TV_A 71 84*5543604aSQin Jian #define PLL_SYS 72 85*5543604aSQin Jian 86*5543604aSQin Jian #define CLK_MAX 73 87*5543604aSQin Jian 88*5543604aSQin Jian #endif 89