1 /* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
2 /*
3  * Copyright (C) STMicroelectronics 2020 - All Rights Reserved
4  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
5  */
6 
7 #ifndef _DT_BINDINGS_STM32MP13_CLKS_H_
8 #define _DT_BINDINGS_STM32MP13_CLKS_H_
9 
10 /* OSCILLATOR clocks */
11 #define CK_HSE		0
12 #define CK_CSI		1
13 #define CK_LSI		2
14 #define CK_LSE		3
15 #define CK_HSI		4
16 #define CK_HSE_DIV2	5
17 
18 /* PLL */
19 #define PLL1		6
20 #define PLL2		7
21 #define PLL3		8
22 #define PLL4		9
23 
24 /* ODF */
25 #define PLL1_P		10
26 #define PLL1_Q		11
27 #define PLL1_R		12
28 #define PLL2_P		13
29 #define PLL2_Q		14
30 #define PLL2_R		15
31 #define PLL3_P		16
32 #define PLL3_Q		17
33 #define PLL3_R		18
34 #define PLL4_P		19
35 #define PLL4_Q		20
36 #define PLL4_R		21
37 
38 #define PCLK1		22
39 #define PCLK2		23
40 #define PCLK3		24
41 #define PCLK4		25
42 #define PCLK5		26
43 #define PCLK6		27
44 
45 /* SYSTEM CLOCK */
46 #define CK_PER		28
47 #define CK_MPU		29
48 #define CK_AXI		30
49 #define CK_MLAHB	31
50 
51 /* BASE TIMER */
52 #define CK_TIMG1	32
53 #define CK_TIMG2	33
54 #define CK_TIMG3	34
55 
56 /* AUX */
57 #define RTC		35
58 
59 /* TRACE & DEBUG clocks */
60 #define CK_DBG		36
61 #define CK_TRACE	37
62 
63 /* MCO clocks */
64 #define CK_MCO1		38
65 #define CK_MCO2		39
66 
67 /*  IP clocks */
68 #define SYSCFG		40
69 #define VREF		41
70 #define DTS		42
71 #define PMBCTRL		43
72 #define HDP		44
73 #define IWDG2		45
74 #define STGENRO		46
75 #define USART1		47
76 #define RTCAPB		48
77 #define TZC		49
78 #define TZPC		50
79 #define IWDG1		51
80 #define BSEC		52
81 #define DMA1		53
82 #define DMA2		54
83 #define DMAMUX1		55
84 #define DMAMUX2		56
85 #define GPIOA		57
86 #define GPIOB		58
87 #define GPIOC		59
88 #define GPIOD		60
89 #define GPIOE		61
90 #define GPIOF		62
91 #define GPIOG		63
92 #define GPIOH		64
93 #define GPIOI		65
94 #define CRYP1		66
95 #define HASH1		67
96 #define BKPSRAM		68
97 #define MDMA		69
98 #define CRC1		70
99 #define USBH		71
100 #define DMA3		72
101 #define TSC		73
102 #define PKA		74
103 #define AXIMC		75
104 #define MCE		76
105 #define ETH1TX		77
106 #define ETH2TX		78
107 #define ETH1RX		79
108 #define ETH2RX		80
109 #define ETH1MAC		81
110 #define ETH2MAC		82
111 #define ETH1STP		83
112 #define ETH2STP		84
113 
114 /* IP clocks with parents */
115 #define SDMMC1_K	85
116 #define SDMMC2_K	86
117 #define ADC1_K		87
118 #define ADC2_K		88
119 #define FMC_K		89
120 #define QSPI_K		90
121 #define RNG1_K		91
122 #define USBPHY_K	92
123 #define STGEN_K		93
124 #define SPDIF_K		94
125 #define SPI1_K		95
126 #define SPI2_K		96
127 #define SPI3_K		97
128 #define SPI4_K		98
129 #define SPI5_K		99
130 #define I2C1_K		100
131 #define I2C2_K		101
132 #define I2C3_K		102
133 #define I2C4_K		103
134 #define I2C5_K		104
135 #define TIM2_K		105
136 #define TIM3_K		106
137 #define TIM4_K		107
138 #define TIM5_K		108
139 #define TIM6_K		109
140 #define TIM7_K		110
141 #define TIM12_K		111
142 #define TIM13_K		112
143 #define TIM14_K		113
144 #define TIM1_K		114
145 #define TIM8_K		115
146 #define TIM15_K		116
147 #define TIM16_K		117
148 #define TIM17_K		118
149 #define LPTIM1_K	119
150 #define LPTIM2_K	120
151 #define LPTIM3_K	121
152 #define LPTIM4_K	122
153 #define LPTIM5_K	123
154 #define USART1_K	124
155 #define USART2_K	125
156 #define USART3_K	126
157 #define UART4_K		127
158 #define UART5_K		128
159 #define USART6_K	129
160 #define UART7_K		130
161 #define UART8_K		131
162 #define DFSDM_K		132
163 #define FDCAN_K		133
164 #define SAI1_K		134
165 #define SAI2_K		135
166 #define ADFSDM_K	136
167 #define USBO_K		137
168 #define LTDC_PX		138
169 #define ETH1CK_K	139
170 #define ETH1PTP_K	140
171 #define ETH2CK_K	141
172 #define ETH2PTP_K	142
173 #define DCMIPP_K	143
174 #define SAES_K		144
175 #define DTS_K		145
176 
177 /* DDR */
178 #define DDRC1		146
179 #define DDRC1LP		147
180 #define DDRC2		148
181 #define DDRC2LP		149
182 #define DDRPHYC		150
183 #define DDRPHYCLP	151
184 #define DDRCAPB		152
185 #define DDRCAPBLP	153
186 #define AXIDCG		154
187 #define DDRPHYCAPB	155
188 #define DDRPHYCAPBLP	156
189 #define DDRPERFM	157
190 
191 #define ADC1		158
192 #define ADC2		159
193 #define SAI1		160
194 #define SAI2		161
195 
196 #define STM32MP1_LAST_CLK 162
197 
198 /* SCMI clock identifiers */
199 #define CK_SCMI_HSE		0
200 #define CK_SCMI_HSI		1
201 #define CK_SCMI_CSI		2
202 #define CK_SCMI_LSE		3
203 #define CK_SCMI_LSI		4
204 #define CK_SCMI_HSE_DIV2	5
205 #define CK_SCMI_PLL2_Q		6
206 #define CK_SCMI_PLL2_R		7
207 #define CK_SCMI_PLL3_P		8
208 #define CK_SCMI_PLL3_Q		9
209 #define CK_SCMI_PLL3_R		10
210 #define CK_SCMI_PLL4_P		11
211 #define CK_SCMI_PLL4_Q		12
212 #define CK_SCMI_PLL4_R		13
213 #define CK_SCMI_MPU		14
214 #define CK_SCMI_AXI		15
215 #define CK_SCMI_MLAHB		16
216 #define CK_SCMI_CKPER		17
217 #define CK_SCMI_PCLK1		18
218 #define CK_SCMI_PCLK2		19
219 #define CK_SCMI_PCLK3		20
220 #define CK_SCMI_PCLK4		21
221 #define CK_SCMI_PCLK5		22
222 #define CK_SCMI_PCLK6		23
223 #define CK_SCMI_CKTIMG1		24
224 #define CK_SCMI_CKTIMG2		25
225 #define CK_SCMI_CKTIMG3		26
226 #define CK_SCMI_RTC		27
227 #define CK_SCMI_RTCAPB		28
228 
229 #endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */
230