1af873fceSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2f8b50363SGabriel Fernandez /*
3f8b50363SGabriel Fernandez  * stm32fx-clock.h
4f8b50363SGabriel Fernandez  *
5f8b50363SGabriel Fernandez  * Copyright (C) 2016 STMicroelectronics
6f8b50363SGabriel Fernandez  * Author: Gabriel Fernandez for STMicroelectronics.
7f8b50363SGabriel Fernandez  */
8f8b50363SGabriel Fernandez 
9f8b50363SGabriel Fernandez /*
10*6853feceSTom Rix  * List of clocks which are not derived from system clock (SYSCLOCK)
11f8b50363SGabriel Fernandez  *
12f8b50363SGabriel Fernandez  * The index of these clocks is the secondary index of DT bindings
13*6853feceSTom Rix  * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
14f8b50363SGabriel Fernandez  *
15f8b50363SGabriel Fernandez  * e.g:
16f8b50363SGabriel Fernandez 	<assigned-clocks = <&rcc 1 CLK_LSE>;
17f8b50363SGabriel Fernandez */
18f8b50363SGabriel Fernandez 
19f8b50363SGabriel Fernandez #ifndef _DT_BINDINGS_CLK_STMFX_H
20f8b50363SGabriel Fernandez #define _DT_BINDINGS_CLK_STMFX_H
21f8b50363SGabriel Fernandez 
22f8b50363SGabriel Fernandez #define SYSTICK			0
23f8b50363SGabriel Fernandez #define FCLK			1
24f8b50363SGabriel Fernandez #define CLK_LSI			2
25f8b50363SGabriel Fernandez #define CLK_LSE			3
26f8b50363SGabriel Fernandez #define CLK_HSE_RTC		4
27f8b50363SGabriel Fernandez #define CLK_RTC			5
28f8b50363SGabriel Fernandez #define PLL_VCO_I2S		6
29f8b50363SGabriel Fernandez #define PLL_VCO_SAI		7
30f8b50363SGabriel Fernandez #define CLK_LCD			8
31f8b50363SGabriel Fernandez #define CLK_I2S			9
32f8b50363SGabriel Fernandez #define CLK_SAI1		10
33f8b50363SGabriel Fernandez #define CLK_SAI2		11
34f8b50363SGabriel Fernandez #define CLK_I2SQ_PDIV		12
35f8b50363SGabriel Fernandez #define CLK_SAIQ_PDIV		13
3652af8557SGabriel Fernandez #define CLK_HSI			14
3752af8557SGabriel Fernandez #define CLK_SYSCLK		15
382f05b6b9SGabriel Fernandez #define CLK_F469_DSI		16
39fa6f3985SGabriel Fernandez 
402f05b6b9SGabriel Fernandez #define END_PRIMARY_CLK		17
41fa6f3985SGabriel Fernandez 
4252af8557SGabriel Fernandez #define CLK_HDMI_CEC		16
4352af8557SGabriel Fernandez #define CLK_SPDIF		17
4452af8557SGabriel Fernandez #define CLK_USART1		18
4552af8557SGabriel Fernandez #define CLK_USART2		19
4652af8557SGabriel Fernandez #define CLK_USART3		20
4752af8557SGabriel Fernandez #define CLK_UART4		21
4852af8557SGabriel Fernandez #define CLK_UART5		22
4952af8557SGabriel Fernandez #define CLK_USART6		23
5052af8557SGabriel Fernandez #define CLK_UART7		24
5152af8557SGabriel Fernandez #define CLK_UART8		25
5252af8557SGabriel Fernandez #define CLK_I2C1		26
5352af8557SGabriel Fernandez #define CLK_I2C2		27
5452af8557SGabriel Fernandez #define CLK_I2C3		28
5552af8557SGabriel Fernandez #define CLK_I2C4		29
5652af8557SGabriel Fernandez #define CLK_LPTIMER		30
57936289f0SGabriel Fernandez #define CLK_PLL_SRC		31
58936289f0SGabriel Fernandez #define CLK_DFSDM1		32
59936289f0SGabriel Fernandez #define CLK_ADFSDM1		33
60936289f0SGabriel Fernandez #define CLK_F769_DSI		34
61936289f0SGabriel Fernandez #define END_PRIMARY_CLK_F7	35
6252af8557SGabriel Fernandez 
63f8b50363SGabriel Fernandez #endif
64