1bf443945SChunyan Zhang // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2bf443945SChunyan Zhang // 3bf443945SChunyan Zhang // Spreadtrum SC9860 platform clocks 4bf443945SChunyan Zhang // 5bf443945SChunyan Zhang // Copyright (C) 2017, Spreadtrum Communications Inc. 6bf443945SChunyan Zhang 7bf443945SChunyan Zhang #ifndef _DT_BINDINGS_CLK_SC9860_H_ 8bf443945SChunyan Zhang #define _DT_BINDINGS_CLK_SC9860_H_ 9bf443945SChunyan Zhang 10bf443945SChunyan Zhang #define CLK_FAC_4M 0 11bf443945SChunyan Zhang #define CLK_FAC_2M 1 12bf443945SChunyan Zhang #define CLK_FAC_1M 2 13bf443945SChunyan Zhang #define CLK_FAC_250K 3 14bf443945SChunyan Zhang #define CLK_FAC_RPLL0_26M 4 15bf443945SChunyan Zhang #define CLK_FAC_RPLL1_26M 5 16bf443945SChunyan Zhang #define CLK_FAC_RCO25M 6 17bf443945SChunyan Zhang #define CLK_FAC_RCO4M 7 18bf443945SChunyan Zhang #define CLK_FAC_RCO2M 8 19bf443945SChunyan Zhang #define CLK_FAC_3K2 9 20bf443945SChunyan Zhang #define CLK_FAC_1K 10 21bf443945SChunyan Zhang #define CLK_MPLL0_GATE 11 22bf443945SChunyan Zhang #define CLK_MPLL1_GATE 12 23bf443945SChunyan Zhang #define CLK_DPLL0_GATE 13 24bf443945SChunyan Zhang #define CLK_DPLL1_GATE 14 25bf443945SChunyan Zhang #define CLK_LTEPLL0_GATE 15 26bf443945SChunyan Zhang #define CLK_TWPLL_GATE 16 27bf443945SChunyan Zhang #define CLK_LTEPLL1_GATE 17 28bf443945SChunyan Zhang #define CLK_RPLL0_GATE 18 29bf443945SChunyan Zhang #define CLK_RPLL1_GATE 19 30bf443945SChunyan Zhang #define CLK_CPPLL_GATE 20 31bf443945SChunyan Zhang #define CLK_GPLL_GATE 21 32bf443945SChunyan Zhang #define CLK_PMU_GATE_NUM (CLK_GPLL_GATE + 1) 33bf443945SChunyan Zhang 34bf443945SChunyan Zhang #define CLK_MPLL0 0 35bf443945SChunyan Zhang #define CLK_MPLL1 1 36bf443945SChunyan Zhang #define CLK_DPLL0 2 37bf443945SChunyan Zhang #define CLK_DPLL1 3 38bf443945SChunyan Zhang #define CLK_RPLL0 4 39bf443945SChunyan Zhang #define CLK_RPLL1 5 40bf443945SChunyan Zhang #define CLK_TWPLL 6 41bf443945SChunyan Zhang #define CLK_LTEPLL0 7 42bf443945SChunyan Zhang #define CLK_LTEPLL1 8 43bf443945SChunyan Zhang #define CLK_GPLL 9 44bf443945SChunyan Zhang #define CLK_CPPLL 10 45bf443945SChunyan Zhang #define CLK_GPLL_42M5 11 46bf443945SChunyan Zhang #define CLK_TWPLL_768M 12 47bf443945SChunyan Zhang #define CLK_TWPLL_384M 13 48bf443945SChunyan Zhang #define CLK_TWPLL_192M 14 49bf443945SChunyan Zhang #define CLK_TWPLL_96M 15 50bf443945SChunyan Zhang #define CLK_TWPLL_48M 16 51bf443945SChunyan Zhang #define CLK_TWPLL_24M 17 52bf443945SChunyan Zhang #define CLK_TWPLL_12M 18 53bf443945SChunyan Zhang #define CLK_TWPLL_512M 19 54bf443945SChunyan Zhang #define CLK_TWPLL_256M 20 55bf443945SChunyan Zhang #define CLK_TWPLL_128M 21 56bf443945SChunyan Zhang #define CLK_TWPLL_64M 22 57bf443945SChunyan Zhang #define CLK_TWPLL_307M2 23 58bf443945SChunyan Zhang #define CLK_TWPLL_153M6 24 59bf443945SChunyan Zhang #define CLK_TWPLL_76M8 25 60bf443945SChunyan Zhang #define CLK_TWPLL_51M2 26 61bf443945SChunyan Zhang #define CLK_TWPLL_38M4 27 62bf443945SChunyan Zhang #define CLK_TWPLL_19M2 28 63bf443945SChunyan Zhang #define CLK_L0_614M4 29 64bf443945SChunyan Zhang #define CLK_L0_409M6 30 65bf443945SChunyan Zhang #define CLK_L0_38M 31 66bf443945SChunyan Zhang #define CLK_L1_38M 32 67bf443945SChunyan Zhang #define CLK_RPLL0_192M 33 68bf443945SChunyan Zhang #define CLK_RPLL0_96M 34 69bf443945SChunyan Zhang #define CLK_RPLL0_48M 35 70bf443945SChunyan Zhang #define CLK_RPLL1_468M 36 71bf443945SChunyan Zhang #define CLK_RPLL1_192M 37 72bf443945SChunyan Zhang #define CLK_RPLL1_96M 38 73bf443945SChunyan Zhang #define CLK_RPLL1_64M 39 74bf443945SChunyan Zhang #define CLK_RPLL1_48M 40 75bf443945SChunyan Zhang #define CLK_DPLL0_50M 41 76bf443945SChunyan Zhang #define CLK_DPLL1_50M 42 77bf443945SChunyan Zhang #define CLK_CPPLL_50M 43 78bf443945SChunyan Zhang #define CLK_M0_39M 44 79bf443945SChunyan Zhang #define CLK_M1_63M 45 80bf443945SChunyan Zhang #define CLK_PLL_NUM (CLK_M1_63M + 1) 81bf443945SChunyan Zhang 82bf443945SChunyan Zhang 83bf443945SChunyan Zhang #define CLK_AP_APB 0 84bf443945SChunyan Zhang #define CLK_AP_USB3 1 85bf443945SChunyan Zhang #define CLK_UART0 2 86bf443945SChunyan Zhang #define CLK_UART1 3 87bf443945SChunyan Zhang #define CLK_UART2 4 88bf443945SChunyan Zhang #define CLK_UART3 5 89bf443945SChunyan Zhang #define CLK_UART4 6 90bf443945SChunyan Zhang #define CLK_I2C0 7 91bf443945SChunyan Zhang #define CLK_I2C1 8 92bf443945SChunyan Zhang #define CLK_I2C2 9 93bf443945SChunyan Zhang #define CLK_I2C3 10 94bf443945SChunyan Zhang #define CLK_I2C4 11 95bf443945SChunyan Zhang #define CLK_I2C5 12 96bf443945SChunyan Zhang #define CLK_SPI0 13 97bf443945SChunyan Zhang #define CLK_SPI1 14 98bf443945SChunyan Zhang #define CLK_SPI2 15 99bf443945SChunyan Zhang #define CLK_SPI3 16 100bf443945SChunyan Zhang #define CLK_IIS0 17 101bf443945SChunyan Zhang #define CLK_IIS1 18 102bf443945SChunyan Zhang #define CLK_IIS2 19 103bf443945SChunyan Zhang #define CLK_IIS3 20 104bf443945SChunyan Zhang #define CLK_AP_CLK_NUM (CLK_IIS3 + 1) 105bf443945SChunyan Zhang 106bf443945SChunyan Zhang #define CLK_AON_APB 0 107bf443945SChunyan Zhang #define CLK_AUX0 1 108bf443945SChunyan Zhang #define CLK_AUX1 2 109bf443945SChunyan Zhang #define CLK_AUX2 3 110bf443945SChunyan Zhang #define CLK_PROBE 4 111bf443945SChunyan Zhang #define CLK_SP_AHB 5 112bf443945SChunyan Zhang #define CLK_CCI 6 113bf443945SChunyan Zhang #define CLK_GIC 7 114bf443945SChunyan Zhang #define CLK_CSSYS 8 115bf443945SChunyan Zhang #define CLK_SDIO0_2X 9 116bf443945SChunyan Zhang #define CLK_SDIO1_2X 10 117bf443945SChunyan Zhang #define CLK_SDIO2_2X 11 118bf443945SChunyan Zhang #define CLK_EMMC_2X 12 119bf443945SChunyan Zhang #define CLK_SDIO0_1X 13 120bf443945SChunyan Zhang #define CLK_SDIO1_1X 14 121bf443945SChunyan Zhang #define CLK_SDIO2_1X 15 122bf443945SChunyan Zhang #define CLK_EMMC_1X 16 123bf443945SChunyan Zhang #define CLK_ADI 17 124bf443945SChunyan Zhang #define CLK_PWM0 18 125bf443945SChunyan Zhang #define CLK_PWM1 19 126bf443945SChunyan Zhang #define CLK_PWM2 20 127bf443945SChunyan Zhang #define CLK_PWM3 21 128bf443945SChunyan Zhang #define CLK_EFUSE 22 129bf443945SChunyan Zhang #define CLK_CM3_UART0 23 130bf443945SChunyan Zhang #define CLK_CM3_UART1 24 131bf443945SChunyan Zhang #define CLK_THM 25 132bf443945SChunyan Zhang #define CLK_CM3_I2C0 26 133bf443945SChunyan Zhang #define CLK_CM3_I2C1 27 134bf443945SChunyan Zhang #define CLK_CM4_SPI 28 135bf443945SChunyan Zhang #define CLK_AON_I2C 29 136bf443945SChunyan Zhang #define CLK_AVS 30 137bf443945SChunyan Zhang #define CLK_CA53_DAP 31 138bf443945SChunyan Zhang #define CLK_CA53_TS 32 139bf443945SChunyan Zhang #define CLK_DJTAG_TCK 33 140bf443945SChunyan Zhang #define CLK_PMU 34 141bf443945SChunyan Zhang #define CLK_PMU_26M 35 142bf443945SChunyan Zhang #define CLK_DEBOUNCE 36 143bf443945SChunyan Zhang #define CLK_OTG2_REF 37 144bf443945SChunyan Zhang #define CLK_USB3_REF 38 145bf443945SChunyan Zhang #define CLK_AP_AXI 39 146bf443945SChunyan Zhang #define CLK_AON_PREDIV_NUM (CLK_AP_AXI + 1) 147bf443945SChunyan Zhang 148bf443945SChunyan Zhang #define CLK_USB3_EB 0 149bf443945SChunyan Zhang #define CLK_USB3_SUSPEND_EB 1 150bf443945SChunyan Zhang #define CLK_USB3_REF_EB 2 151bf443945SChunyan Zhang #define CLK_DMA_EB 3 152bf443945SChunyan Zhang #define CLK_SDIO0_EB 4 153bf443945SChunyan Zhang #define CLK_SDIO1_EB 5 154bf443945SChunyan Zhang #define CLK_SDIO2_EB 6 155bf443945SChunyan Zhang #define CLK_EMMC_EB 7 156bf443945SChunyan Zhang #define CLK_ROM_EB 8 157bf443945SChunyan Zhang #define CLK_BUSMON_EB 9 158bf443945SChunyan Zhang #define CLK_CC63S_EB 10 159bf443945SChunyan Zhang #define CLK_CC63P_EB 11 160bf443945SChunyan Zhang #define CLK_CE0_EB 12 161bf443945SChunyan Zhang #define CLK_CE1_EB 13 162bf443945SChunyan Zhang #define CLK_APAHB_GATE_NUM (CLK_CE1_EB + 1) 163bf443945SChunyan Zhang 164bf443945SChunyan Zhang #define CLK_AVS_LIT_EB 0 165bf443945SChunyan Zhang #define CLK_AVS_BIG_EB 1 166bf443945SChunyan Zhang #define CLK_AP_INTC5_EB 2 167bf443945SChunyan Zhang #define CLK_GPIO_EB 3 168bf443945SChunyan Zhang #define CLK_PWM0_EB 4 169bf443945SChunyan Zhang #define CLK_PWM1_EB 5 170bf443945SChunyan Zhang #define CLK_PWM2_EB 6 171bf443945SChunyan Zhang #define CLK_PWM3_EB 7 172bf443945SChunyan Zhang #define CLK_KPD_EB 8 173bf443945SChunyan Zhang #define CLK_AON_SYS_EB 9 174bf443945SChunyan Zhang #define CLK_AP_SYS_EB 10 175bf443945SChunyan Zhang #define CLK_AON_TMR_EB 11 176bf443945SChunyan Zhang #define CLK_AP_TMR0_EB 12 177bf443945SChunyan Zhang #define CLK_EFUSE_EB 13 178bf443945SChunyan Zhang #define CLK_EIC_EB 14 179bf443945SChunyan Zhang #define CLK_PUB1_REG_EB 15 180bf443945SChunyan Zhang #define CLK_ADI_EB 16 181bf443945SChunyan Zhang #define CLK_AP_INTC0_EB 17 182bf443945SChunyan Zhang #define CLK_AP_INTC1_EB 18 183bf443945SChunyan Zhang #define CLK_AP_INTC2_EB 19 184bf443945SChunyan Zhang #define CLK_AP_INTC3_EB 20 185bf443945SChunyan Zhang #define CLK_AP_INTC4_EB 21 186bf443945SChunyan Zhang #define CLK_SPLK_EB 22 187bf443945SChunyan Zhang #define CLK_MSPI_EB 23 188bf443945SChunyan Zhang #define CLK_PUB0_REG_EB 24 189bf443945SChunyan Zhang #define CLK_PIN_EB 25 190bf443945SChunyan Zhang #define CLK_AON_CKG_EB 26 191bf443945SChunyan Zhang #define CLK_GPU_EB 27 192bf443945SChunyan Zhang #define CLK_APCPU_TS0_EB 28 193bf443945SChunyan Zhang #define CLK_APCPU_TS1_EB 29 194bf443945SChunyan Zhang #define CLK_DAP_EB 30 195bf443945SChunyan Zhang #define CLK_I2C_EB 31 196bf443945SChunyan Zhang #define CLK_PMU_EB 32 197bf443945SChunyan Zhang #define CLK_THM_EB 33 198bf443945SChunyan Zhang #define CLK_AUX0_EB 34 199bf443945SChunyan Zhang #define CLK_AUX1_EB 35 200bf443945SChunyan Zhang #define CLK_AUX2_EB 36 201bf443945SChunyan Zhang #define CLK_PROBE_EB 37 202bf443945SChunyan Zhang #define CLK_GPU0_AVS_EB 38 203bf443945SChunyan Zhang #define CLK_GPU1_AVS_EB 39 204bf443945SChunyan Zhang #define CLK_APCPU_WDG_EB 40 205bf443945SChunyan Zhang #define CLK_AP_TMR1_EB 41 206bf443945SChunyan Zhang #define CLK_AP_TMR2_EB 42 207bf443945SChunyan Zhang #define CLK_DISP_EMC_EB 43 208bf443945SChunyan Zhang #define CLK_ZIP_EMC_EB 44 209bf443945SChunyan Zhang #define CLK_GSP_EMC_EB 45 210bf443945SChunyan Zhang #define CLK_OSC_AON_EB 46 211bf443945SChunyan Zhang #define CLK_LVDS_TRX_EB 47 212bf443945SChunyan Zhang #define CLK_LVDS_TCXO_EB 48 213bf443945SChunyan Zhang #define CLK_MDAR_EB 49 214bf443945SChunyan Zhang #define CLK_RTC4M0_CAL_EB 50 215bf443945SChunyan Zhang #define CLK_RCT100M_CAL_EB 51 216bf443945SChunyan Zhang #define CLK_DJTAG_EB 52 217bf443945SChunyan Zhang #define CLK_MBOX_EB 53 218bf443945SChunyan Zhang #define CLK_AON_DMA_EB 54 219bf443945SChunyan Zhang #define CLK_DBG_EMC_EB 55 220bf443945SChunyan Zhang #define CLK_LVDS_PLL_DIV_EN 56 221bf443945SChunyan Zhang #define CLK_DEF_EB 57 222bf443945SChunyan Zhang #define CLK_AON_APB_RSV0 58 223bf443945SChunyan Zhang #define CLK_ORP_JTAG_EB 59 224bf443945SChunyan Zhang #define CLK_VSP_EB 60 225bf443945SChunyan Zhang #define CLK_CAM_EB 61 226bf443945SChunyan Zhang #define CLK_DISP_EB 62 227bf443945SChunyan Zhang #define CLK_DBG_AXI_IF_EB 63 228bf443945SChunyan Zhang #define CLK_SDIO0_2X_EN 64 229bf443945SChunyan Zhang #define CLK_SDIO1_2X_EN 65 230bf443945SChunyan Zhang #define CLK_SDIO2_2X_EN 66 231bf443945SChunyan Zhang #define CLK_EMMC_2X_EN 67 232f7c14dd5SChunyan Zhang #define CLK_ARCH_RTC_EB 68 233f7c14dd5SChunyan Zhang #define CLK_KPB_RTC_EB 69 234f7c14dd5SChunyan Zhang #define CLK_AON_SYST_RTC_EB 70 235f7c14dd5SChunyan Zhang #define CLK_AP_SYST_RTC_EB 71 236f7c14dd5SChunyan Zhang #define CLK_AON_TMR_RTC_EB 72 237f7c14dd5SChunyan Zhang #define CLK_AP_TMR0_RTC_EB 73 238f7c14dd5SChunyan Zhang #define CLK_EIC_RTC_EB 74 239f7c14dd5SChunyan Zhang #define CLK_EIC_RTCDV5_EB 75 240f7c14dd5SChunyan Zhang #define CLK_AP_WDG_RTC_EB 76 241f7c14dd5SChunyan Zhang #define CLK_AP_TMR1_RTC_EB 77 242f7c14dd5SChunyan Zhang #define CLK_AP_TMR2_RTC_EB 78 243f7c14dd5SChunyan Zhang #define CLK_DCXO_TMR_RTC_EB 79 244f7c14dd5SChunyan Zhang #define CLK_BB_CAL_RTC_EB 80 245f7c14dd5SChunyan Zhang #define CLK_AVS_BIG_RTC_EB 81 246f7c14dd5SChunyan Zhang #define CLK_AVS_LIT_RTC_EB 82 247f7c14dd5SChunyan Zhang #define CLK_AVS_GPU0_RTC_EB 83 248f7c14dd5SChunyan Zhang #define CLK_AVS_GPU1_RTC_EB 84 249f7c14dd5SChunyan Zhang #define CLK_GPU_TS_EB 85 250f7c14dd5SChunyan Zhang #define CLK_RTCDV10_EB 86 251f7c14dd5SChunyan Zhang #define CLK_AON_GATE_NUM (CLK_RTCDV10_EB + 1) 252bf443945SChunyan Zhang 253bf443945SChunyan Zhang #define CLK_LIT_MCU 0 254bf443945SChunyan Zhang #define CLK_BIG_MCU 1 255bf443945SChunyan Zhang #define CLK_AONSECURE_NUM (CLK_BIG_MCU + 1) 256bf443945SChunyan Zhang 257bf443945SChunyan Zhang #define CLK_AGCP_IIS0_EB 0 258bf443945SChunyan Zhang #define CLK_AGCP_IIS1_EB 1 259bf443945SChunyan Zhang #define CLK_AGCP_IIS2_EB 2 260bf443945SChunyan Zhang #define CLK_AGCP_IIS3_EB 3 261bf443945SChunyan Zhang #define CLK_AGCP_UART_EB 4 262bf443945SChunyan Zhang #define CLK_AGCP_DMACP_EB 5 263bf443945SChunyan Zhang #define CLK_AGCP_DMAAP_EB 6 264bf443945SChunyan Zhang #define CLK_AGCP_ARC48K_EB 7 265bf443945SChunyan Zhang #define CLK_AGCP_SRC44P1K_EB 8 266bf443945SChunyan Zhang #define CLK_AGCP_MCDT_EB 9 267bf443945SChunyan Zhang #define CLK_AGCP_VBCIFD_EB 10 268bf443945SChunyan Zhang #define CLK_AGCP_VBC_EB 11 269bf443945SChunyan Zhang #define CLK_AGCP_SPINLOCK_EB 12 270bf443945SChunyan Zhang #define CLK_AGCP_ICU_EB 13 271bf443945SChunyan Zhang #define CLK_AGCP_AP_ASHB_EB 14 272bf443945SChunyan Zhang #define CLK_AGCP_CP_ASHB_EB 15 273bf443945SChunyan Zhang #define CLK_AGCP_AUD_EB 16 274bf443945SChunyan Zhang #define CLK_AGCP_AUDIF_EB 17 275bf443945SChunyan Zhang #define CLK_AGCP_GATE_NUM (CLK_AGCP_AUDIF_EB + 1) 276bf443945SChunyan Zhang 277bf443945SChunyan Zhang #define CLK_GPU 0 278bf443945SChunyan Zhang #define CLK_GPU_NUM (CLK_GPU + 1) 279bf443945SChunyan Zhang 280bf443945SChunyan Zhang #define CLK_AHB_VSP 0 281bf443945SChunyan Zhang #define CLK_VSP 1 282bf443945SChunyan Zhang #define CLK_VSP_ENC 2 283bf443945SChunyan Zhang #define CLK_VPP 3 284bf443945SChunyan Zhang #define CLK_VSP_26M 4 285bf443945SChunyan Zhang #define CLK_VSP_NUM (CLK_VSP_26M + 1) 286bf443945SChunyan Zhang 287bf443945SChunyan Zhang #define CLK_VSP_DEC_EB 0 288bf443945SChunyan Zhang #define CLK_VSP_CKG_EB 1 289bf443945SChunyan Zhang #define CLK_VSP_MMU_EB 2 290bf443945SChunyan Zhang #define CLK_VSP_ENC_EB 3 291bf443945SChunyan Zhang #define CLK_VPP_EB 4 292bf443945SChunyan Zhang #define CLK_VSP_26M_EB 5 293bf443945SChunyan Zhang #define CLK_VSP_AXI_GATE 6 294bf443945SChunyan Zhang #define CLK_VSP_ENC_GATE 7 295bf443945SChunyan Zhang #define CLK_VPP_AXI_GATE 8 296bf443945SChunyan Zhang #define CLK_VSP_BM_GATE 9 297bf443945SChunyan Zhang #define CLK_VSP_ENC_BM_GATE 10 298bf443945SChunyan Zhang #define CLK_VPP_BM_GATE 11 299bf443945SChunyan Zhang #define CLK_VSP_GATE_NUM (CLK_VPP_BM_GATE + 1) 300bf443945SChunyan Zhang 301bf443945SChunyan Zhang #define CLK_AHB_CAM 0 302bf443945SChunyan Zhang #define CLK_SENSOR0 1 303bf443945SChunyan Zhang #define CLK_SENSOR1 2 304bf443945SChunyan Zhang #define CLK_SENSOR2 3 305bf443945SChunyan Zhang #define CLK_MIPI_CSI0_EB 4 306bf443945SChunyan Zhang #define CLK_MIPI_CSI1_EB 5 307bf443945SChunyan Zhang #define CLK_CAM_NUM (CLK_MIPI_CSI1_EB + 1) 308bf443945SChunyan Zhang 309bf443945SChunyan Zhang #define CLK_DCAM0_EB 0 310bf443945SChunyan Zhang #define CLK_DCAM1_EB 1 311bf443945SChunyan Zhang #define CLK_ISP0_EB 2 312bf443945SChunyan Zhang #define CLK_CSI0_EB 3 313bf443945SChunyan Zhang #define CLK_CSI1_EB 4 314bf443945SChunyan Zhang #define CLK_JPG0_EB 5 315bf443945SChunyan Zhang #define CLK_JPG1_EB 6 316bf443945SChunyan Zhang #define CLK_CAM_CKG_EB 7 317bf443945SChunyan Zhang #define CLK_CAM_MMU_EB 8 318bf443945SChunyan Zhang #define CLK_ISP1_EB 9 319bf443945SChunyan Zhang #define CLK_CPP_EB 10 320bf443945SChunyan Zhang #define CLK_MMU_PF_EB 11 321bf443945SChunyan Zhang #define CLK_ISP2_EB 12 322bf443945SChunyan Zhang #define CLK_DCAM2ISP_IF_EB 13 323bf443945SChunyan Zhang #define CLK_ISP2DCAM_IF_EB 14 324bf443945SChunyan Zhang #define CLK_ISP_LCLK_EB 15 325bf443945SChunyan Zhang #define CLK_ISP_ICLK_EB 16 326bf443945SChunyan Zhang #define CLK_ISP_MCLK_EB 17 327bf443945SChunyan Zhang #define CLK_ISP_PCLK_EB 18 328bf443945SChunyan Zhang #define CLK_ISP_ISP2DCAM_EB 19 329bf443945SChunyan Zhang #define CLK_DCAM0_IF_EB 20 330bf443945SChunyan Zhang #define CLK_CLK26M_IF_EB 21 331bf443945SChunyan Zhang #define CLK_CPHY0_GATE 22 332bf443945SChunyan Zhang #define CLK_MIPI_CSI0_GATE 23 333bf443945SChunyan Zhang #define CLK_CPHY1_GATE 24 334bf443945SChunyan Zhang #define CLK_MIPI_CSI1 25 335bf443945SChunyan Zhang #define CLK_DCAM0_AXI_GATE 26 336bf443945SChunyan Zhang #define CLK_DCAM1_AXI_GATE 27 337bf443945SChunyan Zhang #define CLK_SENSOR0_GATE 28 338bf443945SChunyan Zhang #define CLK_SENSOR1_GATE 29 339bf443945SChunyan Zhang #define CLK_JPG0_AXI_GATE 30 340bf443945SChunyan Zhang #define CLK_GPG1_AXI_GATE 31 341bf443945SChunyan Zhang #define CLK_ISP0_AXI_GATE 32 342bf443945SChunyan Zhang #define CLK_ISP1_AXI_GATE 33 343bf443945SChunyan Zhang #define CLK_ISP2_AXI_GATE 34 344bf443945SChunyan Zhang #define CLK_CPP_AXI_GATE 35 345bf443945SChunyan Zhang #define CLK_D0_IF_AXI_GATE 36 346bf443945SChunyan Zhang #define CLK_D2I_IF_AXI_GATE 37 347bf443945SChunyan Zhang #define CLK_I2D_IF_AXI_GATE 38 348bf443945SChunyan Zhang #define CLK_SPARE_AXI_GATE 39 349bf443945SChunyan Zhang #define CLK_SENSOR2_GATE 40 350bf443945SChunyan Zhang #define CLK_D0IF_IN_D_EN 41 351bf443945SChunyan Zhang #define CLK_D1IF_IN_D_EN 42 352bf443945SChunyan Zhang #define CLK_D0IF_IN_D2I_EN 43 353bf443945SChunyan Zhang #define CLK_D1IF_IN_D2I_EN 44 354bf443945SChunyan Zhang #define CLK_IA_IN_D2I_EN 45 355bf443945SChunyan Zhang #define CLK_IB_IN_D2I_EN 46 356bf443945SChunyan Zhang #define CLK_IC_IN_D2I_EN 47 357bf443945SChunyan Zhang #define CLK_IA_IN_I_EN 48 358bf443945SChunyan Zhang #define CLK_IB_IN_I_EN 49 359bf443945SChunyan Zhang #define CLK_IC_IN_I_EN 50 360bf443945SChunyan Zhang #define CLK_CAM_GATE_NUM (CLK_IC_IN_I_EN + 1) 361bf443945SChunyan Zhang 362bf443945SChunyan Zhang #define CLK_AHB_DISP 0 363bf443945SChunyan Zhang #define CLK_DISPC0_DPI 1 364bf443945SChunyan Zhang #define CLK_DISPC1_DPI 2 365bf443945SChunyan Zhang #define CLK_DISP_NUM (CLK_DISPC1_DPI + 1) 366bf443945SChunyan Zhang 367bf443945SChunyan Zhang #define CLK_DISPC0_EB 0 368bf443945SChunyan Zhang #define CLK_DISPC1_EB 1 369bf443945SChunyan Zhang #define CLK_DISPC_MMU_EB 2 370bf443945SChunyan Zhang #define CLK_GSP0_EB 3 371bf443945SChunyan Zhang #define CLK_GSP1_EB 4 372bf443945SChunyan Zhang #define CLK_GSP0_MMU_EB 5 373bf443945SChunyan Zhang #define CLK_GSP1_MMU_EB 6 374bf443945SChunyan Zhang #define CLK_DSI0_EB 7 375bf443945SChunyan Zhang #define CLK_DSI1_EB 8 376bf443945SChunyan Zhang #define CLK_DISP_CKG_EB 9 377bf443945SChunyan Zhang #define CLK_DISP_GPU_EB 10 378bf443945SChunyan Zhang #define CLK_GPU_MTX_EB 11 379bf443945SChunyan Zhang #define CLK_GSP_MTX_EB 12 380bf443945SChunyan Zhang #define CLK_TMC_MTX_EB 13 381bf443945SChunyan Zhang #define CLK_DISPC_MTX_EB 14 382bf443945SChunyan Zhang #define CLK_DPHY0_GATE 15 383bf443945SChunyan Zhang #define CLK_DPHY1_GATE 16 384bf443945SChunyan Zhang #define CLK_GSP0_A_GATE 17 385bf443945SChunyan Zhang #define CLK_GSP1_A_GATE 18 386bf443945SChunyan Zhang #define CLK_GSP0_F_GATE 19 387bf443945SChunyan Zhang #define CLK_GSP1_F_GATE 20 388bf443945SChunyan Zhang #define CLK_D_MTX_F_GATE 21 389bf443945SChunyan Zhang #define CLK_D_MTX_A_GATE 22 390bf443945SChunyan Zhang #define CLK_D_NOC_F_GATE 23 391bf443945SChunyan Zhang #define CLK_D_NOC_A_GATE 24 392bf443945SChunyan Zhang #define CLK_GSP_MTX_F_GATE 25 393bf443945SChunyan Zhang #define CLK_GSP_MTX_A_GATE 26 394bf443945SChunyan Zhang #define CLK_GSP_NOC_F_GATE 27 395bf443945SChunyan Zhang #define CLK_GSP_NOC_A_GATE 28 396bf443945SChunyan Zhang #define CLK_DISPM0IDLE_GATE 29 397bf443945SChunyan Zhang #define CLK_GSPM0IDLE_GATE 30 398bf443945SChunyan Zhang #define CLK_DISP_GATE_NUM (CLK_GSPM0IDLE_GATE + 1) 399bf443945SChunyan Zhang 400bf443945SChunyan Zhang #define CLK_SIM0_EB 0 401bf443945SChunyan Zhang #define CLK_IIS0_EB 1 402bf443945SChunyan Zhang #define CLK_IIS1_EB 2 403bf443945SChunyan Zhang #define CLK_IIS2_EB 3 404bf443945SChunyan Zhang #define CLK_IIS3_EB 4 405bf443945SChunyan Zhang #define CLK_SPI0_EB 5 406bf443945SChunyan Zhang #define CLK_SPI1_EB 6 407bf443945SChunyan Zhang #define CLK_SPI2_EB 7 408bf443945SChunyan Zhang #define CLK_I2C0_EB 8 409bf443945SChunyan Zhang #define CLK_I2C1_EB 9 410bf443945SChunyan Zhang #define CLK_I2C2_EB 10 411bf443945SChunyan Zhang #define CLK_I2C3_EB 11 412bf443945SChunyan Zhang #define CLK_I2C4_EB 12 413bf443945SChunyan Zhang #define CLK_I2C5_EB 13 414bf443945SChunyan Zhang #define CLK_UART0_EB 14 415bf443945SChunyan Zhang #define CLK_UART1_EB 15 416bf443945SChunyan Zhang #define CLK_UART2_EB 16 417bf443945SChunyan Zhang #define CLK_UART3_EB 17 418bf443945SChunyan Zhang #define CLK_UART4_EB 18 419bf443945SChunyan Zhang #define CLK_AP_CKG_EB 19 420bf443945SChunyan Zhang #define CLK_SPI3_EB 20 421bf443945SChunyan Zhang #define CLK_APAPB_GATE_NUM (CLK_SPI3_EB + 1) 422bf443945SChunyan Zhang 423bf443945SChunyan Zhang #endif /* _DT_BINDINGS_CLK_SC9860_H_ */ 424