1*efc91ae4SZong Li /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2*efc91ae4SZong Li /*
3*efc91ae4SZong Li  * Copyright (C) 2019 SiFive, Inc.
4*efc91ae4SZong Li  * Wesley Terpstra
5*efc91ae4SZong Li  * Paul Walmsley
6*efc91ae4SZong Li  * Zong Li
7*efc91ae4SZong Li  */
8*efc91ae4SZong Li 
9*efc91ae4SZong Li #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
10*efc91ae4SZong Li #define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
11*efc91ae4SZong Li 
12*efc91ae4SZong Li /* Clock indexes for use by Device Tree data and the PRCI driver */
13*efc91ae4SZong Li 
14*efc91ae4SZong Li #define PRCI_CLK_COREPLL	       0
15*efc91ae4SZong Li #define PRCI_CLK_DDRPLL		       1
16*efc91ae4SZong Li #define PRCI_CLK_GEMGXLPLL	       2
17*efc91ae4SZong Li #define PRCI_CLK_DVFSCOREPLL	       3
18*efc91ae4SZong Li #define PRCI_CLK_HFPCLKPLL	       4
19*efc91ae4SZong Li #define PRCI_CLK_CLTXPLL	       5
20*efc91ae4SZong Li #define PRCI_CLK_TLCLK		       6
21*efc91ae4SZong Li #define PRCI_CLK_PCLK		       7
22*efc91ae4SZong Li 
23*efc91ae4SZong Li #endif	/* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */
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