1efc91ae4SZong Li /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2efc91ae4SZong Li /* 3efc91ae4SZong Li * Copyright (C) 2019 SiFive, Inc. 4efc91ae4SZong Li * Wesley Terpstra 5efc91ae4SZong Li * Paul Walmsley 6efc91ae4SZong Li * Zong Li 7efc91ae4SZong Li */ 8efc91ae4SZong Li 9efc91ae4SZong Li #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H 10efc91ae4SZong Li #define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H 11efc91ae4SZong Li 12efc91ae4SZong Li /* Clock indexes for use by Device Tree data and the PRCI driver */ 13efc91ae4SZong Li 14*0493692bSZong Li #define FU740_PRCI_CLK_COREPLL 0 15*0493692bSZong Li #define FU740_PRCI_CLK_DDRPLL 1 16*0493692bSZong Li #define FU740_PRCI_CLK_GEMGXLPLL 2 17*0493692bSZong Li #define FU740_PRCI_CLK_DVFSCOREPLL 3 18*0493692bSZong Li #define FU740_PRCI_CLK_HFPCLKPLL 4 19*0493692bSZong Li #define FU740_PRCI_CLK_CLTXPLL 5 20*0493692bSZong Li #define FU740_PRCI_CLK_TLCLK 6 21*0493692bSZong Li #define FU740_PRCI_CLK_PCLK 7 22*0493692bSZong Li #define FU740_PRCI_CLK_PCIE_AUX 8 23efc91ae4SZong Li 24efc91ae4SZong Li #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ 25