1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 29978f28fSTomasz Figa /* 39978f28fSTomasz Figa * Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com> 49978f28fSTomasz Figa * 59978f28fSTomasz Figa * This header provides constants for Samsung audio subsystem 69978f28fSTomasz Figa * clock controller. 79978f28fSTomasz Figa * 89978f28fSTomasz Figa * The constants defined in this header are being used in dts 99978f28fSTomasz Figa * and s5pv210 audss driver. 109978f28fSTomasz Figa */ 119978f28fSTomasz Figa 129978f28fSTomasz Figa #ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H 139978f28fSTomasz Figa #define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H 149978f28fSTomasz Figa 159978f28fSTomasz Figa #define CLK_MOUT_AUDSS 0 169978f28fSTomasz Figa #define CLK_MOUT_I2S_A 1 179978f28fSTomasz Figa 189978f28fSTomasz Figa #define CLK_DOUT_AUD_BUS 2 199978f28fSTomasz Figa #define CLK_DOUT_I2S_A 3 209978f28fSTomasz Figa 219978f28fSTomasz Figa #define CLK_I2S 4 229978f28fSTomasz Figa #define CLK_HCLK_I2S 5 239978f28fSTomasz Figa #define CLK_HCLK_UART 6 249978f28fSTomasz Figa #define CLK_HCLK_HWA 7 259978f28fSTomasz Figa #define CLK_HCLK_DMA 8 269978f28fSTomasz Figa #define CLK_HCLK_BUF 9 279978f28fSTomasz Figa #define CLK_HCLK_RP 10 289978f28fSTomasz Figa 299978f28fSTomasz Figa #define AUDSS_MAX_CLKS 11 309978f28fSTomasz Figa 319978f28fSTomasz Figa #endif 32