1 /* 2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 3 * Author: Shawn Lin <shawn.lin@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 18 19 /* pll id */ 20 #define PLL_APLL 0 21 #define PLL_DPLL 1 22 #define PLL_GPLL 2 23 #define ARMCLK 3 24 25 /* sclk gates (special clocks) */ 26 #define SCLK_SPI0 65 27 #define SCLK_NANDC 67 28 #define SCLK_SDMMC 68 29 #define SCLK_SDIO 69 30 #define SCLK_EMMC 71 31 #define SCLK_UART0 72 32 #define SCLK_UART1 73 33 #define SCLK_UART2 74 34 #define SCLK_I2S0 75 35 #define SCLK_I2S1 76 36 #define SCLK_I2S2 77 37 #define SCLK_TIMER0 78 38 #define SCLK_TIMER1 79 39 #define SCLK_SFC 80 40 #define SCLK_SDMMC_DRV 81 41 #define SCLK_SDIO_DRV 82 42 #define SCLK_EMMC_DRV 83 43 #define SCLK_SDMMC_SAMPLE 84 44 #define SCLK_SDIO_SAMPLE 85 45 #define SCLK_EMMC_SAMPLE 86 46 #define SCLK_VENC_CORE 87 47 #define SCLK_HEVC_CORE 88 48 #define SCLK_HEVC_CABAC 89 49 #define SCLK_PWM0_PMU 90 50 #define SCLK_I2C0_PMU 91 51 #define SCLK_WIFI 92 52 #define SCLK_CIFOUT 93 53 #define SCLK_MIPI_CSI_OUT 94 54 #define SCLK_CIF0 95 55 #define SCLK_CIF1 96 56 #define SCLK_CIF2 97 57 #define SCLK_CIF3 98 58 #define SCLK_DSP 99 59 #define SCLK_DSP_IOP 100 60 #define SCLK_DSP_EPP 101 61 #define SCLK_DSP_EDP 102 62 #define SCLK_DSP_EDAP 103 63 #define SCLK_CVBS_HOST 104 64 #define SCLK_HDMI_SFR 105 65 #define SCLK_HDMI_CEC 106 66 #define SCLK_CRYPTO 107 67 #define SCLK_SPI 108 68 #define SCLK_SARADC 109 69 #define SCLK_TSADC 110 70 #define SCLK_MAC_PRE 111 71 #define SCLK_MAC 112 72 #define SCLK_MAC_RX 113 73 #define SCLK_MAC_REF 114 74 #define SCLK_MAC_REFOUT 115 75 #define SCLK_DSP_PFM 116 76 #define SCLK_RGA 117 77 #define SCLK_I2C1 118 78 #define SCLK_I2C2 119 79 #define SCLK_I2C3 120 80 #define SCLK_PWM 121 81 #define SCLK_ISP 122 82 #define SCLK_USBPHY 123 83 #define SCLK_I2S0_SRC 124 84 #define SCLK_I2S1_SRC 125 85 #define SCLK_I2S2_SRC 126 86 #define SCLK_UART0_SRC 127 87 #define SCLK_UART1_SRC 128 88 #define SCLK_UART2_SRC 129 89 90 #define DCLK_VOP_SRC 185 91 #define DCLK_HDMIPHY 186 92 #define DCLK_VOP 187 93 94 /* aclk gates */ 95 #define ACLK_DMAC 192 96 #define ACLK_PRE 193 97 #define ACLK_CORE 194 98 #define ACLK_ENMCORE 195 99 #define ACLK_RKVENC 196 100 #define ACLK_RKVDEC 197 101 #define ACLK_VPU 198 102 #define ACLK_CIF0 199 103 #define ACLK_VIO0 200 104 #define ACLK_VIO1 201 105 #define ACLK_VOP 202 106 #define ACLK_IEP 203 107 #define ACLK_RGA 204 108 #define ACLK_ISP 205 109 #define ACLK_CIF1 206 110 #define ACLK_CIF2 207 111 #define ACLK_CIF3 208 112 #define ACLK_PERI 209 113 #define ACLK_GMAC 210 114 115 /* pclk gates */ 116 #define PCLK_GPIO1 256 117 #define PCLK_GPIO2 257 118 #define PCLK_GPIO3 258 119 #define PCLK_GRF 259 120 #define PCLK_I2C1 260 121 #define PCLK_I2C2 261 122 #define PCLK_I2C3 262 123 #define PCLK_SPI 263 124 #define PCLK_SFC 264 125 #define PCLK_UART0 265 126 #define PCLK_UART1 266 127 #define PCLK_UART2 267 128 #define PCLK_TSADC 268 129 #define PCLK_PWM 269 130 #define PCLK_TIMER 270 131 #define PCLK_PERI 271 132 #define PCLK_GPIO0_PMU 272 133 #define PCLK_I2C0_PMU 273 134 #define PCLK_PWM0_PMU 274 135 #define PCLK_ISP 275 136 #define PCLK_VIO 276 137 #define PCLK_MIPI_DSI 277 138 #define PCLK_HDMI_CTRL 278 139 #define PCLK_SARADC 279 140 #define PCLK_DSP_CFG 280 141 #define PCLK_BUS 281 142 #define PCLK_EFUSE0 282 143 #define PCLK_EFUSE1 283 144 #define PCLK_WDT 284 145 #define PCLK_GMAC 285 146 147 /* hclk gates */ 148 #define HCLK_I2S0_8CH 320 149 #define HCLK_I2S1_2CH 321 150 #define HCLK_I2S2_2CH 322 151 #define HCLK_NANDC 323 152 #define HCLK_SDMMC 324 153 #define HCLK_SDIO 325 154 #define HCLK_EMMC 326 155 #define HCLK_PERI 327 156 #define HCLK_SFC 328 157 #define HCLK_RKVENC 329 158 #define HCLK_RKVDEC 330 159 #define HCLK_CIF0 331 160 #define HCLK_VIO 332 161 #define HCLK_VOP 333 162 #define HCLK_IEP 334 163 #define HCLK_RGA 335 164 #define HCLK_ISP 336 165 #define HCLK_CRYPTO_MST 337 166 #define HCLK_CRYPTO_SLV 338 167 #define HCLK_HOST0 339 168 #define HCLK_OTG 340 169 #define HCLK_CIF1 341 170 #define HCLK_CIF2 342 171 #define HCLK_CIF3 343 172 #define HCLK_BUS 344 173 #define HCLK_VPU 345 174 175 #define CLK_NR_CLKS (HCLK_VPU + 1) 176 177 /* reset id */ 178 #define SRST_CORE_PO_AD 0 179 #define SRST_CORE_AD 1 180 #define SRST_L2_AD 2 181 #define SRST_CPU_NIU_AD 3 182 #define SRST_CORE_PO 4 183 #define SRST_CORE 5 184 #define SRST_L2 6 185 #define SRST_CORE_DBG 8 186 #define PRST_DBG 9 187 #define RST_DAP 10 188 #define PRST_DBG_NIU 11 189 #define ARST_STRC_SYS_AD 15 190 191 #define SRST_DDRPHY_CLKDIV 16 192 #define SRST_DDRPHY 17 193 #define PRST_DDRPHY 18 194 #define PRST_HDMIPHY 19 195 #define PRST_VDACPHY 20 196 #define PRST_VADCPHY 21 197 #define PRST_MIPI_CSI_PHY 22 198 #define PRST_MIPI_DSI_PHY 23 199 #define PRST_ACODEC 24 200 #define ARST_BUS_NIU 25 201 #define PRST_TOP_NIU 26 202 #define ARST_INTMEM 27 203 #define HRST_ROM 28 204 #define ARST_DMAC 29 205 #define SRST_MSCH_NIU 30 206 #define PRST_MSCH_NIU 31 207 208 #define PRST_DDRUPCTL 32 209 #define NRST_DDRUPCTL 33 210 #define PRST_DDRMON 34 211 #define HRST_I2S0_8CH 35 212 #define MRST_I2S0_8CH 36 213 #define HRST_I2S1_2CH 37 214 #define MRST_IS21_2CH 38 215 #define HRST_I2S2_2CH 39 216 #define MRST_I2S2_2CH 40 217 #define HRST_CRYPTO 41 218 #define SRST_CRYPTO 42 219 #define PRST_SPI 43 220 #define SRST_SPI 44 221 #define PRST_UART0 45 222 #define PRST_UART1 46 223 #define PRST_UART2 47 224 225 #define SRST_UART0 48 226 #define SRST_UART1 49 227 #define SRST_UART2 50 228 #define PRST_I2C1 51 229 #define PRST_I2C2 52 230 #define PRST_I2C3 53 231 #define SRST_I2C1 54 232 #define SRST_I2C2 55 233 #define SRST_I2C3 56 234 #define PRST_PWM1 58 235 #define SRST_PWM1 60 236 #define PRST_WDT 61 237 #define PRST_GPIO1 62 238 #define PRST_GPIO2 63 239 240 #define PRST_GPIO3 64 241 #define PRST_GRF 65 242 #define PRST_EFUSE 66 243 #define PRST_EFUSE512 67 244 #define PRST_TIMER0 68 245 #define SRST_TIMER0 69 246 #define SRST_TIMER1 70 247 #define PRST_TSADC 71 248 #define SRST_TSADC 72 249 #define PRST_SARADC 73 250 #define SRST_SARADC 74 251 #define HRST_SYSBUS 75 252 #define PRST_USBGRF 76 253 254 #define ARST_PERIPH_NIU 80 255 #define HRST_PERIPH_NIU 81 256 #define PRST_PERIPH_NIU 82 257 #define HRST_PERIPH 83 258 #define HRST_SDMMC 84 259 #define HRST_SDIO 85 260 #define HRST_EMMC 86 261 #define HRST_NANDC 87 262 #define NRST_NANDC 88 263 #define HRST_SFC 89 264 #define SRST_SFC 90 265 #define ARST_GMAC 91 266 #define HRST_OTG 92 267 #define SRST_OTG 93 268 #define SRST_OTG_ADP 94 269 #define HRST_HOST0 95 270 271 #define HRST_HOST0_AUX 96 272 #define HRST_HOST0_ARB 97 273 #define SRST_HOST0_EHCIPHY 98 274 #define SRST_HOST0_UTMI 99 275 #define SRST_USBPOR 100 276 #define SRST_UTMI0 101 277 #define SRST_UTMI1 102 278 279 #define ARST_VIO0_NIU 102 280 #define ARST_VIO1_NIU 103 281 #define HRST_VIO_NIU 104 282 #define PRST_VIO_NIU 105 283 #define ARST_VOP 106 284 #define HRST_VOP 107 285 #define DRST_VOP 108 286 #define ARST_IEP 109 287 #define HRST_IEP 110 288 #define ARST_RGA 111 289 #define HRST_RGA 112 290 #define SRST_RGA 113 291 #define PRST_CVBS 114 292 #define PRST_HDMI 115 293 #define SRST_HDMI 116 294 #define PRST_MIPI_DSI 117 295 296 #define ARST_ISP_NIU 118 297 #define HRST_ISP_NIU 119 298 #define HRST_ISP 120 299 #define SRST_ISP 121 300 #define ARST_VIP0 122 301 #define HRST_VIP0 123 302 #define PRST_VIP0 124 303 #define ARST_VIP1 125 304 #define HRST_VIP1 126 305 #define PRST_VIP1 127 306 #define ARST_VIP2 128 307 #define HRST_VIP2 129 308 #define PRST_VIP2 120 309 #define ARST_VIP3 121 310 #define HRST_VIP3 122 311 #define PRST_VIP4 123 312 313 #define PRST_CIF1TO4 124 314 #define SRST_CVBS_CLK 125 315 #define HRST_CVBS 126 316 317 #define ARST_VPU_NIU 140 318 #define HRST_VPU_NIU 141 319 #define ARST_VPU 142 320 #define HRST_VPU 143 321 #define ARST_RKVDEC_NIU 144 322 #define HRST_RKVDEC_NIU 145 323 #define ARST_RKVDEC 146 324 #define HRST_RKVDEC 147 325 #define SRST_RKVDEC_CABAC 148 326 #define SRST_RKVDEC_CORE 149 327 #define ARST_RKVENC_NIU 150 328 #define HRST_RKVENC_NIU 151 329 #define ARST_RKVENC 152 330 #define HRST_RKVENC 153 331 #define SRST_RKVENC_CORE 154 332 333 #define SRST_DSP_CORE 156 334 #define SRST_DSP_SYS 157 335 #define SRST_DSP_GLOBAL 158 336 #define SRST_DSP_OECM 159 337 #define PRST_DSP_IOP_NIU 160 338 #define ARST_DSP_EPP_NIU 161 339 #define ARST_DSP_EDP_NIU 162 340 #define PRST_DSP_DBG_NIU 163 341 #define PRST_DSP_CFG_NIU 164 342 #define PRST_DSP_GRF 165 343 #define PRST_DSP_MAILBOX 166 344 #define PRST_DSP_INTC 167 345 #define PRST_DSP_PFM_MON 169 346 #define SRST_DSP_PFM_MON 170 347 #define ARST_DSP_EDAP_NIU 171 348 349 #define SRST_PMU 172 350 #define SRST_PMU_I2C0 173 351 #define PRST_PMU_I2C0 174 352 #define PRST_PMU_GPIO0 175 353 #define PRST_PMU_INTMEM 176 354 #define PRST_PMU_PWM0 177 355 #define SRST_PMU_PWM0 178 356 #define PRST_PMU_GRF 179 357 #define SRST_PMU_NIU 180 358 #define SRST_PMU_PVTM 181 359 #define ARST_DSP_EDP_PERF 184 360 #define ARST_DSP_EPP_PERF 185 361 362 #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ 363