1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ 2 /* 3 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 4 * Author: Finley Xiao <finley.xiao@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H 9 10 /* pmucru-clocks indices */ 11 12 /* pll clocks */ 13 #define PLL_GPLL 1 14 15 /* sclk (special clocks) */ 16 #define CLK_OSC0_DIV32K 2 17 #define CLK_RTC32K 3 18 #define CLK_WIFI_DIV 4 19 #define CLK_WIFI_OSC0 5 20 #define CLK_WIFI 6 21 #define CLK_PMU 7 22 #define SCLK_UART1_DIV 8 23 #define SCLK_UART1_FRACDIV 9 24 #define SCLK_UART1_MUX 10 25 #define SCLK_UART1 11 26 #define CLK_I2C0 12 27 #define CLK_I2C2 13 28 #define CLK_CAPTURE_PWM0 14 29 #define CLK_PWM0 15 30 #define CLK_CAPTURE_PWM1 16 31 #define CLK_PWM1 17 32 #define CLK_SPI0 18 33 #define DBCLK_GPIO0 19 34 #define CLK_PMUPVTM 20 35 #define CLK_CORE_PMUPVTM 21 36 #define CLK_REF12M 22 37 #define CLK_USBPHY_OTG_REF 23 38 #define CLK_USBPHY_HOST_REF 24 39 #define CLK_REF24M 25 40 #define CLK_MIPIDSIPHY_REF 26 41 42 /* pclk */ 43 #define PCLK_PDPMU 30 44 #define PCLK_PMU 31 45 #define PCLK_UART1 32 46 #define PCLK_I2C0 33 47 #define PCLK_I2C2 34 48 #define PCLK_PWM0 35 49 #define PCLK_PWM1 36 50 #define PCLK_SPI0 37 51 #define PCLK_GPIO0 38 52 #define PCLK_PMUSGRF 39 53 #define PCLK_PMUGRF 40 54 #define PCLK_PMUCRU 41 55 #define PCLK_CHIPVEROTP 42 56 #define PCLK_PDPMU_NIU 43 57 #define PCLK_PMUPVTM 44 58 #define PCLK_SCRKEYGEN 45 59 60 #define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1) 61 62 /* cru-clocks indices */ 63 64 /* pll clocks */ 65 #define PLL_APLL 1 66 #define PLL_DPLL 2 67 #define PLL_CPLL 3 68 #define PLL_HPLL 4 69 70 /* sclk (special clocks) */ 71 #define ARMCLK 5 72 #define USB480M 6 73 #define CLK_CORE_CPUPVTM 7 74 #define CLK_CPUPVTM 8 75 #define CLK_SCR1 9 76 #define CLK_SCR1_CORE 10 77 #define CLK_SCR1_RTC 11 78 #define CLK_SCR1_JTAG 12 79 #define SCLK_UART0_DIV 13 80 #define SCLK_UART0_FRAC 14 81 #define SCLK_UART0_MUX 15 82 #define SCLK_UART0 16 83 #define SCLK_UART2_DIV 17 84 #define SCLK_UART2_FRAC 18 85 #define SCLK_UART2_MUX 19 86 #define SCLK_UART2 20 87 #define SCLK_UART3_DIV 21 88 #define SCLK_UART3_FRAC 22 89 #define SCLK_UART3_MUX 23 90 #define SCLK_UART3 24 91 #define SCLK_UART4_DIV 25 92 #define SCLK_UART4_FRAC 26 93 #define SCLK_UART4_MUX 27 94 #define SCLK_UART4 28 95 #define SCLK_UART5_DIV 29 96 #define SCLK_UART5_FRAC 30 97 #define SCLK_UART5_MUX 31 98 #define SCLK_UART5 32 99 #define CLK_I2C1 33 100 #define CLK_I2C3 34 101 #define CLK_I2C4 35 102 #define CLK_I2C5 36 103 #define CLK_SPI1 37 104 #define CLK_CAPTURE_PWM2 38 105 #define CLK_PWM2 39 106 #define DBCLK_GPIO1 40 107 #define DBCLK_GPIO2 41 108 #define DBCLK_GPIO3 42 109 #define DBCLK_GPIO4 43 110 #define CLK_SARADC 44 111 #define CLK_TIMER0 45 112 #define CLK_TIMER1 46 113 #define CLK_TIMER2 47 114 #define CLK_TIMER3 48 115 #define CLK_TIMER4 49 116 #define CLK_TIMER5 50 117 #define CLK_CAN 51 118 #define CLK_NPU_TSADC 52 119 #define CLK_NPU_TSADCPHY 53 120 #define CLK_CPU_TSADC 54 121 #define CLK_CPU_TSADCPHY 55 122 #define CLK_CRYPTO_CORE 56 123 #define CLK_CRYPTO_PKA 57 124 #define MCLK_I2S0_TX_DIV 58 125 #define MCLK_I2S0_TX_FRACDIV 59 126 #define MCLK_I2S0_TX_MUX 60 127 #define MCLK_I2S0_TX 61 128 #define MCLK_I2S0_RX_DIV 62 129 #define MCLK_I2S0_RX_FRACDIV 63 130 #define MCLK_I2S0_RX_MUX 64 131 #define MCLK_I2S0_RX 65 132 #define MCLK_I2S0_TX_OUT2IO 66 133 #define MCLK_I2S0_RX_OUT2IO 67 134 #define MCLK_I2S1_DIV 68 135 #define MCLK_I2S1_FRACDIV 69 136 #define MCLK_I2S1_MUX 70 137 #define MCLK_I2S1 71 138 #define MCLK_I2S1_OUT2IO 72 139 #define MCLK_I2S2_DIV 73 140 #define MCLK_I2S2_FRACDIV 74 141 #define MCLK_I2S2_MUX 75 142 #define MCLK_I2S2 76 143 #define MCLK_I2S2_OUT2IO 77 144 #define MCLK_PDM 78 145 #define SCLK_ADUPWM_DIV 79 146 #define SCLK_AUDPWM_FRACDIV 80 147 #define SCLK_AUDPWM_MUX 81 148 #define SCLK_AUDPWM 82 149 #define CLK_ACDCDIG_ADC 83 150 #define CLK_ACDCDIG_DAC 84 151 #define CLK_ACDCDIG_I2C 85 152 #define CLK_VENC_CORE 86 153 #define CLK_VDEC_CORE 87 154 #define CLK_VDEC_CA 88 155 #define CLK_VDEC_HEVC_CA 89 156 #define CLK_RGA_CORE 90 157 #define CLK_IEP_CORE 91 158 #define CLK_ISP_DIV 92 159 #define CLK_ISP_NP5 93 160 #define CLK_ISP_NUX 94 161 #define CLK_ISP 95 162 #define CLK_CIF_OUT_DIV 96 163 #define CLK_CIF_OUT_FRACDIV 97 164 #define CLK_CIF_OUT_MUX 98 165 #define CLK_CIF_OUT 99 166 #define CLK_MIPICSI_OUT_DIV 100 167 #define CLK_MIPICSI_OUT_FRACDIV 101 168 #define CLK_MIPICSI_OUT_MUX 102 169 #define CLK_MIPICSI_OUT 103 170 #define CLK_ISPP_DIV 104 171 #define CLK_ISPP_NP5 105 172 #define CLK_ISPP_NUX 106 173 #define CLK_ISPP 107 174 #define CLK_SDMMC 108 175 #define SCLK_SDMMC_DRV 109 176 #define SCLK_SDMMC_SAMPLE 110 177 #define CLK_SDIO 111 178 #define SCLK_SDIO_DRV 112 179 #define SCLK_SDIO_SAMPLE 113 180 #define CLK_EMMC 114 181 #define SCLK_EMMC_DRV 115 182 #define SCLK_EMMC_SAMPLE 116 183 #define CLK_NANDC 117 184 #define SCLK_SFC 118 185 #define CLK_USBHOST_UTMI_OHCI 119 186 #define CLK_USBOTG_REF 120 187 #define CLK_GMAC_DIV 121 188 #define CLK_GMAC_RGMII_M0 122 189 #define CLK_GMAC_SRC_M0 123 190 #define CLK_GMAC_RGMII_M1 124 191 #define CLK_GMAC_SRC_M1 125 192 #define CLK_GMAC_SRC 126 193 #define CLK_GMAC_REF 127 194 #define CLK_GMAC_TX_SRC 128 195 #define CLK_GMAC_TX_DIV5 129 196 #define CLK_GMAC_TX_DIV50 130 197 #define RGMII_MODE_CLK 131 198 #define CLK_GMAC_RX_SRC 132 199 #define CLK_GMAC_RX_DIV2 133 200 #define CLK_GMAC_RX_DIV20 134 201 #define RMII_MODE_CLK 135 202 #define CLK_GMAC_TX_RX 136 203 #define CLK_GMAC_PTPREF 137 204 #define CLK_GMAC_ETHERNET_OUT 138 205 #define CLK_DDRPHY 139 206 #define CLK_DDR_MON 140 207 #define TMCLK_DDR_MON 141 208 #define CLK_NPU_DIV 142 209 #define CLK_NPU_NP5 143 210 #define CLK_CORE_NPU 144 211 #define CLK_CORE_NPUPVTM 145 212 #define CLK_NPUPVTM 146 213 #define SCLK_DDRCLK 147 214 #define CLK_OTP 148 215 216 /* dclk */ 217 #define DCLK_DECOM 150 218 #define DCLK_VOP_DIV 151 219 #define DCLK_VOP_FRACDIV 152 220 #define DCLK_VOP_MUX 153 221 #define DCLK_VOP 154 222 #define DCLK_CIF 155 223 #define DCLK_CIFLITE 156 224 225 /* aclk */ 226 #define ACLK_PDBUS 160 227 #define ACLK_DMAC 161 228 #define ACLK_DCF 162 229 #define ACLK_SPINLOCK 163 230 #define ACLK_DECOM 164 231 #define ACLK_PDCRYPTO 165 232 #define ACLK_CRYPTO 166 233 #define ACLK_PDVEPU 167 234 #define ACLK_VENC 168 235 #define ACLK_PDVDEC 169 236 #define ACLK_PDJPEG 170 237 #define ACLK_VDEC 171 238 #define ACLK_JPEG 172 239 #define ACLK_PDVO 173 240 #define ACLK_RGA 174 241 #define ACLK_VOP 175 242 #define ACLK_IEP 176 243 #define ACLK_PDVI_DIV 177 244 #define ACLK_PDVI_NP5 178 245 #define ACLK_PDVI 179 246 #define ACLK_ISP 180 247 #define ACLK_CIF 181 248 #define ACLK_CIFLITE 182 249 #define ACLK_PDISPP_DIV 183 250 #define ACLK_PDISPP_NP5 184 251 #define ACLK_PDISPP 185 252 #define ACLK_ISPP 186 253 #define ACLK_PDPHP 187 254 #define ACLK_PDUSB 188 255 #define ACLK_USBOTG 189 256 #define ACLK_PDGMAC 190 257 #define ACLK_GMAC 191 258 #define ACLK_PDNPU_DIV 192 259 #define ACLK_PDNPU_NP5 193 260 #define ACLK_PDNPU 194 261 #define ACLK_NPU 195 262 263 /* hclk */ 264 #define HCLK_PDCORE_NIU 200 265 #define HCLK_PDUSB 201 266 #define HCLK_PDCRYPTO 202 267 #define HCLK_CRYPTO 203 268 #define HCLK_PDAUDIO 204 269 #define HCLK_I2S0 205 270 #define HCLK_I2S1 206 271 #define HCLK_I2S2 207 272 #define HCLK_PDM 208 273 #define HCLK_AUDPWM 209 274 #define HCLK_PDVEPU 210 275 #define HCLK_VENC 211 276 #define HCLK_PDVDEC 212 277 #define HCLK_PDJPEG 213 278 #define HCLK_VDEC 214 279 #define HCLK_JPEG 215 280 #define HCLK_PDVO 216 281 #define HCLK_RGA 217 282 #define HCLK_VOP 218 283 #define HCLK_IEP 219 284 #define HCLK_PDVI 220 285 #define HCLK_ISP 221 286 #define HCLK_CIF 222 287 #define HCLK_CIFLITE 223 288 #define HCLK_PDISPP 224 289 #define HCLK_ISPP 225 290 #define HCLK_PDPHP 226 291 #define HCLK_PDSDMMC 227 292 #define HCLK_SDMMC 228 293 #define HCLK_PDSDIO 229 294 #define HCLK_SDIO 230 295 #define HCLK_PDNVM 231 296 #define HCLK_EMMC 232 297 #define HCLK_NANDC 233 298 #define HCLK_SFC 234 299 #define HCLK_SFCXIP 235 300 #define HCLK_PDBUS 236 301 #define HCLK_USBHOST 237 302 #define HCLK_USBHOST_ARB 238 303 #define HCLK_PDNPU 239 304 #define HCLK_NPU 240 305 306 /* pclk */ 307 #define PCLK_CPUPVTM 245 308 #define PCLK_PDBUS 246 309 #define PCLK_DCF 247 310 #define PCLK_WDT 248 311 #define PCLK_MAILBOX 249 312 #define PCLK_UART0 250 313 #define PCLK_UART2 251 314 #define PCLK_UART3 252 315 #define PCLK_UART4 253 316 #define PCLK_UART5 254 317 #define PCLK_I2C1 255 318 #define PCLK_I2C3 256 319 #define PCLK_I2C4 257 320 #define PCLK_I2C5 258 321 #define PCLK_SPI1 259 322 #define PCLK_PWM2 261 323 #define PCLK_GPIO1 262 324 #define PCLK_GPIO2 263 325 #define PCLK_GPIO3 264 326 #define PCLK_GPIO4 265 327 #define PCLK_SARADC 266 328 #define PCLK_TIMER 267 329 #define PCLK_DECOM 268 330 #define PCLK_CAN 269 331 #define PCLK_NPU_TSADC 270 332 #define PCLK_CPU_TSADC 271 333 #define PCLK_ACDCDIG 272 334 #define PCLK_PDVO 273 335 #define PCLK_DSIHOST 274 336 #define PCLK_PDVI 275 337 #define PCLK_CSIHOST 276 338 #define PCLK_PDGMAC 277 339 #define PCLK_GMAC 278 340 #define PCLK_PDDDR 279 341 #define PCLK_DDR_MON 280 342 #define PCLK_PDNPU 281 343 #define PCLK_NPUPVTM 282 344 #define PCLK_PDTOP 283 345 #define PCLK_TOPCRU 284 346 #define PCLK_TOPGRF 285 347 #define PCLK_CPUEMADET 286 348 #define PCLK_DDRPHY 287 349 #define PCLK_DSIPHY 289 350 #define PCLK_CSIPHY0 290 351 #define PCLK_CSIPHY1 291 352 #define PCLK_USBPHY_HOST 292 353 #define PCLK_USBPHY_OTG 293 354 #define PCLK_OTP 294 355 356 #define CLK_NR_CLKS (PCLK_OTP + 1) 357 358 /* pmu soft-reset indices */ 359 360 /* pmu_cru_softrst_con0 */ 361 #define SRST_PDPMU_NIU_P 0 362 #define SRST_PMU_SGRF_P 1 363 #define SRST_PMU_SGRF_REMAP_P 2 364 #define SRST_I2C0_P 3 365 #define SRST_I2C0 4 366 #define SRST_I2C2_P 7 367 #define SRST_I2C2 8 368 #define SRST_UART1_P 9 369 #define SRST_UART1 10 370 #define SRST_PWM0_P 11 371 #define SRST_PWM0 12 372 #define SRST_PWM1_P 13 373 #define SRST_PWM1 14 374 #define SRST_DDR_FAIL_SAFE 15 375 376 /* pmu_cru_softrst_con1 */ 377 #define SRST_GPIO0_P 17 378 #define SRST_GPIO0_DB 18 379 #define SRST_SPI0_P 19 380 #define SRST_SPI0 20 381 #define SRST_PMUGRF_P 21 382 #define SRST_CHIPVEROTP_P 22 383 #define SRST_PMUPVTM 24 384 #define SRST_PMUPVTM_P 25 385 #define SRST_PMUCRU_P 30 386 387 /* soft-reset indices */ 388 389 /* cru_softrst_con0 */ 390 #define SRST_CORE0_PO 0 391 #define SRST_CORE1_PO 1 392 #define SRST_CORE2_PO 2 393 #define SRST_CORE3_PO 3 394 #define SRST_CORE0 4 395 #define SRST_CORE1 5 396 #define SRST_CORE2 6 397 #define SRST_CORE3 7 398 #define SRST_CORE0_DBG 8 399 #define SRST_CORE1_DBG 9 400 #define SRST_CORE2_DBG 10 401 #define SRST_CORE3_DBG 11 402 #define SRST_NL2 12 403 #define SRST_CORE_NIU_A 13 404 #define SRST_DBG_DAPLITE_P 14 405 #define SRST_DAPLITE_P 15 406 407 /* cru_softrst_con1 */ 408 #define SRST_PDBUS_NIU1_A 16 409 #define SRST_PDBUS_NIU1_H 17 410 #define SRST_PDBUS_NIU1_P 18 411 #define SRST_PDBUS_NIU2_A 19 412 #define SRST_PDBUS_NIU2_H 20 413 #define SRST_PDBUS_NIU3_A 21 414 #define SRST_PDBUS_NIU3_H 22 415 #define SRST_PDBUS_HOLD_NIU1_A 23 416 #define SRST_DBG_NIU_P 24 417 #define SRST_PDCORE_NIIU_H 25 418 #define SRST_MUC_NIU 26 419 #define SRST_DCF_A 29 420 #define SRST_DCF_P 30 421 #define SRST_SYSTEM_SRAM_A 31 422 423 /* cru_softrst_con2 */ 424 #define SRST_I2C1_P 32 425 #define SRST_I2C1 33 426 #define SRST_I2C3_P 34 427 #define SRST_I2C3 35 428 #define SRST_I2C4_P 36 429 #define SRST_I2C4 37 430 #define SRST_I2C5_P 38 431 #define SRST_I2C5 39 432 #define SRST_SPI1_P 40 433 #define SRST_SPI1 41 434 #define SRST_MCU_CORE 42 435 #define SRST_PWM2_P 44 436 #define SRST_PWM2 45 437 #define SRST_SPINLOCK_A 46 438 439 /* cru_softrst_con3 */ 440 #define SRST_UART0_P 48 441 #define SRST_UART0 49 442 #define SRST_UART2_P 50 443 #define SRST_UART2 51 444 #define SRST_UART3_P 52 445 #define SRST_UART3 53 446 #define SRST_UART4_P 54 447 #define SRST_UART4 55 448 #define SRST_UART5_P 56 449 #define SRST_UART5 57 450 #define SRST_WDT_P 58 451 #define SRST_SARADC_P 59 452 #define SRST_GRF_P 61 453 #define SRST_TIMER_P 62 454 #define SRST_MAILBOX_P 63 455 456 /* cru_softrst_con4 */ 457 #define SRST_TIMER0 64 458 #define SRST_TIMER1 65 459 #define SRST_TIMER2 66 460 #define SRST_TIMER3 67 461 #define SRST_TIMER4 68 462 #define SRST_TIMER5 69 463 #define SRST_INTMUX_P 70 464 #define SRST_GPIO1_P 72 465 #define SRST_GPIO1_DB 73 466 #define SRST_GPIO2_P 74 467 #define SRST_GPIO2_DB 75 468 #define SRST_GPIO3_P 76 469 #define SRST_GPIO3_DB 77 470 #define SRST_GPIO4_P 78 471 #define SRST_GPIO4_DB 79 472 473 /* cru_softrst_con5 */ 474 #define SRST_CAN_P 80 475 #define SRST_CAN 81 476 #define SRST_DECOM_A 85 477 #define SRST_DECOM_P 86 478 #define SRST_DECOM_D 87 479 #define SRST_PDCRYPTO_NIU_A 88 480 #define SRST_PDCRYPTO_NIU_H 89 481 #define SRST_CRYPTO_A 90 482 #define SRST_CRYPTO_H 91 483 #define SRST_CRYPTO_CORE 92 484 #define SRST_CRYPTO_PKA 93 485 #define SRST_SGRF_P 95 486 487 /* cru_softrst_con6 */ 488 #define SRST_PDAUDIO_NIU_H 96 489 #define SRST_PDAUDIO_NIU_P 97 490 #define SRST_I2S0_H 98 491 #define SRST_I2S0_TX_M 99 492 #define SRST_I2S0_RX_M 100 493 #define SRST_I2S1_H 101 494 #define SRST_I2S1_M 102 495 #define SRST_I2S2_H 103 496 #define SRST_I2S2_M 104 497 #define SRST_PDM_H 105 498 #define SRST_PDM_M 106 499 #define SRST_AUDPWM_H 107 500 #define SRST_AUDPWM 108 501 #define SRST_ACDCDIG_P 109 502 #define SRST_ACDCDIG 110 503 504 /* cru_softrst_con7 */ 505 #define SRST_PDVEPU_NIU_A 112 506 #define SRST_PDVEPU_NIU_H 113 507 #define SRST_VENC_A 114 508 #define SRST_VENC_H 115 509 #define SRST_VENC_CORE 116 510 #define SRST_PDVDEC_NIU_A 117 511 #define SRST_PDVDEC_NIU_H 118 512 #define SRST_VDEC_A 119 513 #define SRST_VDEC_H 120 514 #define SRST_VDEC_CORE 121 515 #define SRST_VDEC_CA 122 516 #define SRST_VDEC_HEVC_CA 123 517 #define SRST_PDJPEG_NIU_A 124 518 #define SRST_PDJPEG_NIU_H 125 519 #define SRST_JPEG_A 126 520 #define SRST_JPEG_H 127 521 522 /* cru_softrst_con8 */ 523 #define SRST_PDVO_NIU_A 128 524 #define SRST_PDVO_NIU_H 129 525 #define SRST_PDVO_NIU_P 130 526 #define SRST_RGA_A 131 527 #define SRST_RGA_H 132 528 #define SRST_RGA_CORE 133 529 #define SRST_VOP_A 134 530 #define SRST_VOP_H 135 531 #define SRST_VOP_D 136 532 #define SRST_TXBYTEHS_DSIHOST 137 533 #define SRST_DSIHOST_P 138 534 #define SRST_IEP_A 139 535 #define SRST_IEP_H 140 536 #define SRST_IEP_CORE 141 537 #define SRST_ISP_RX_P 142 538 539 /* cru_softrst_con9 */ 540 #define SRST_PDVI_NIU_A 144 541 #define SRST_PDVI_NIU_H 145 542 #define SRST_PDVI_NIU_P 146 543 #define SRST_ISP 147 544 #define SRST_CIF_A 148 545 #define SRST_CIF_H 149 546 #define SRST_CIF_D 150 547 #define SRST_CIF_P 151 548 #define SRST_CIF_I 152 549 #define SRST_CIF_RX_P 153 550 #define SRST_PDISPP_NIU_A 154 551 #define SRST_PDISPP_NIU_H 155 552 #define SRST_ISPP_A 156 553 #define SRST_ISPP_H 157 554 #define SRST_ISPP 158 555 #define SRST_CSIHOST_P 159 556 557 /* cru_softrst_con10 */ 558 #define SRST_PDPHPMID_NIU_A 160 559 #define SRST_PDPHPMID_NIU_H 161 560 #define SRST_PDNVM_NIU_H 163 561 #define SRST_SDMMC_H 164 562 #define SRST_SDIO_H 165 563 #define SRST_EMMC_H 166 564 #define SRST_SFC_H 167 565 #define SRST_SFCXIP_H 168 566 #define SRST_SFC 169 567 #define SRST_NANDC_H 170 568 #define SRST_NANDC 171 569 #define SRST_PDSDMMC_H 173 570 #define SRST_PDSDIO_H 174 571 572 /* cru_softrst_con11 */ 573 #define SRST_PDUSB_NIU_A 176 574 #define SRST_PDUSB_NIU_H 177 575 #define SRST_USBHOST_H 178 576 #define SRST_USBHOST_ARB_H 179 577 #define SRST_USBHOST_UTMI 180 578 #define SRST_USBOTG_A 181 579 #define SRST_USBPHY_OTG_P 182 580 #define SRST_USBPHY_HOST_P 183 581 #define SRST_USBPHYPOR_OTG 184 582 #define SRST_USBPHYPOR_HOST 185 583 #define SRST_PDGMAC_NIU_A 188 584 #define SRST_PDGMAC_NIU_P 189 585 #define SRST_GMAC_A 190 586 587 /* cru_softrst_con12 */ 588 #define SRST_DDR_DFICTL_P 193 589 #define SRST_DDR_MON_P 194 590 #define SRST_DDR_STANDBY_P 195 591 #define SRST_DDR_GRF_P 196 592 #define SRST_DDR_MSCH_P 197 593 #define SRST_DDR_SPLIT_A 198 594 #define SRST_DDR_MSCH 199 595 #define SRST_DDR_DFICTL 202 596 #define SRST_DDR_STANDBY 203 597 #define SRST_NPUMCU_NIU 205 598 #define SRST_DDRPHY_P 206 599 #define SRST_DDRPHY 207 600 601 /* cru_softrst_con13 */ 602 #define SRST_PDNPU_NIU_A 208 603 #define SRST_PDNPU_NIU_H 209 604 #define SRST_PDNPU_NIU_P 210 605 #define SRST_NPU_A 211 606 #define SRST_NPU_H 212 607 #define SRST_NPU 213 608 #define SRST_NPUPVTM_P 214 609 #define SRST_NPUPVTM 215 610 #define SRST_NPU_TSADC_P 216 611 #define SRST_NPU_TSADC 217 612 #define SRST_NPU_TSADCPHY 218 613 #define SRST_CIFLITE_A 220 614 #define SRST_CIFLITE_H 221 615 #define SRST_CIFLITE_D 222 616 #define SRST_CIFLITE_RX_P 223 617 618 /* cru_softrst_con14 */ 619 #define SRST_TOPNIU_P 224 620 #define SRST_TOPCRU_P 225 621 #define SRST_TOPGRF_P 226 622 #define SRST_CPUEMADET_P 227 623 #define SRST_CSIPHY0_P 228 624 #define SRST_CSIPHY1_P 229 625 #define SRST_DSIPHY_P 230 626 #define SRST_CPU_TSADC_P 232 627 #define SRST_CPU_TSADC 233 628 #define SRST_CPU_TSADCPHY 234 629 #define SRST_CPUPVTM_P 235 630 #define SRST_CPUPVTM 236 631 632 #endif 633