1 /*
2  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3  * Author: Elaine <zhangqing@rock-chips.com>
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
18 
19 /* core clocks */
20 #define PLL_APLL		1
21 #define PLL_DPLL		2
22 #define PLL_CPLL		3
23 #define PLL_GPLL		4
24 #define PLL_NPLL		5
25 #define ARMCLK			6
26 
27 /* sclk gates (special clocks) */
28 #define SCLK_RTC32K		30
29 #define SCLK_SDMMC_EXT		31
30 #define SCLK_SPI		32
31 #define SCLK_SDMMC		33
32 #define SCLK_SDIO		34
33 #define SCLK_EMMC		35
34 #define SCLK_TSADC		36
35 #define SCLK_SARADC		37
36 #define SCLK_UART0		38
37 #define SCLK_UART1		39
38 #define SCLK_UART2		40
39 #define SCLK_I2S0		41
40 #define SCLK_I2S1		42
41 #define SCLK_I2S2		43
42 #define SCLK_I2S1_OUT		44
43 #define SCLK_I2S2_OUT		45
44 #define SCLK_SPDIF		46
45 #define SCLK_TIMER0		47
46 #define SCLK_TIMER1		48
47 #define SCLK_TIMER2		49
48 #define SCLK_TIMER3		50
49 #define SCLK_TIMER4		51
50 #define SCLK_TIMER5		52
51 #define SCLK_WIFI		53
52 #define SCLK_CIF_OUT		54
53 #define SCLK_I2C0		55
54 #define SCLK_I2C1		56
55 #define SCLK_I2C2		57
56 #define SCLK_I2C3		58
57 #define SCLK_CRYPTO		59
58 #define SCLK_PWM		60
59 #define SCLK_PDM		61
60 #define SCLK_EFUSE		62
61 #define SCLK_OTP		63
62 #define SCLK_DDRCLK		64
63 #define SCLK_VDEC_CABAC		65
64 #define SCLK_VDEC_CORE		66
65 #define SCLK_VENC_DSP		67
66 #define SCLK_VENC_CORE		68
67 #define SCLK_RGA		69
68 #define SCLK_HDMI_SFC		70
69 #define SCLK_HDMI_CEC		71
70 #define SCLK_USB3_REF		72
71 #define SCLK_USB3_SUSPEND	73
72 #define SCLK_SDMMC_DRV		74
73 #define SCLK_SDIO_DRV		75
74 #define SCLK_EMMC_DRV		76
75 #define SCLK_SDMMC_EXT_DRV	77
76 #define SCLK_SDMMC_SAMPLE	78
77 #define SCLK_SDIO_SAMPLE	79
78 #define SCLK_EMMC_SAMPLE	80
79 #define SCLK_SDMMC_EXT_SAMPLE	81
80 #define SCLK_VOP		82
81 #define SCLK_MAC2PHY_RXTX	83
82 #define SCLK_MAC2PHY_SRC	84
83 #define SCLK_MAC2PHY_REF	85
84 #define SCLK_MAC2PHY_OUT	86
85 #define SCLK_MAC2IO_RX		87
86 #define SCLK_MAC2IO_TX		88
87 #define SCLK_MAC2IO_REFOUT	89
88 #define SCLK_MAC2IO_REF		90
89 #define SCLK_MAC2IO_OUT		91
90 #define SCLK_TSP		92
91 #define SCLK_HSADC_TSP		93
92 #define SCLK_USB3PHY_REF	94
93 #define SCLK_REF_USB3OTG	95
94 #define SCLK_USB3OTG_REF	96
95 #define SCLK_USB3OTG_SUSPEND	97
96 #define SCLK_REF_USB3OTG_SRC	98
97 #define SCLK_MAC2IO_SRC		99
98 #define SCLK_MAC2IO		100
99 #define SCLK_MAC2PHY		101
100 #define SCLK_MAC2IO_EXT		102
101 
102 /* dclk gates */
103 #define DCLK_LCDC		120
104 #define DCLK_HDMIPHY		121
105 #define HDMIPHY			122
106 #define USB480M			123
107 #define DCLK_LCDC_SRC		124
108 
109 /* aclk gates */
110 #define ACLK_AXISRAM		130
111 #define ACLK_VOP_PRE		131
112 #define ACLK_USB3OTG		132
113 #define ACLK_RGA_PRE		133
114 #define ACLK_DMAC		134
115 #define ACLK_GPU		135
116 #define ACLK_BUS_PRE		136
117 #define ACLK_PERI_PRE		137
118 #define ACLK_RKVDEC_PRE		138
119 #define ACLK_RKVDEC		139
120 #define ACLK_RKVENC		140
121 #define ACLK_VPU_PRE		141
122 #define ACLK_VIO_PRE		142
123 #define ACLK_VPU		143
124 #define ACLK_VIO		144
125 #define ACLK_VOP		145
126 #define ACLK_GMAC		146
127 #define ACLK_H265		147
128 #define ACLK_H264		148
129 #define ACLK_MAC2PHY		149
130 #define ACLK_MAC2IO		150
131 #define ACLK_DCF		151
132 #define ACLK_TSP		152
133 #define ACLK_PERI		153
134 #define ACLK_RGA		154
135 #define ACLK_IEP		155
136 #define ACLK_CIF		156
137 #define ACLK_HDCP		157
138 
139 /* pclk gates */
140 #define PCLK_GPIO0		200
141 #define PCLK_GPIO1		201
142 #define PCLK_GPIO2		202
143 #define PCLK_GPIO3		203
144 #define PCLK_GRF		204
145 #define PCLK_I2C0		205
146 #define PCLK_I2C1		206
147 #define PCLK_I2C2		207
148 #define PCLK_I2C3		208
149 #define PCLK_SPI		209
150 #define PCLK_UART0		210
151 #define PCLK_UART1		211
152 #define PCLK_UART2		212
153 #define PCLK_TSADC		213
154 #define PCLK_PWM		214
155 #define PCLK_TIMER		215
156 #define PCLK_BUS_PRE		216
157 #define PCLK_PERI_PRE		217
158 #define PCLK_HDMI_CTRL		218
159 #define PCLK_HDMI_PHY		219
160 #define PCLK_GMAC		220
161 #define PCLK_H265		221
162 #define PCLK_MAC2PHY		222
163 #define PCLK_MAC2IO		223
164 #define PCLK_USB3PHY_OTG	224
165 #define PCLK_USB3PHY_PIPE	225
166 #define PCLK_USB3_GRF		226
167 #define PCLK_USB2_GRF		227
168 #define PCLK_HDMIPHY		228
169 #define PCLK_DDR		229
170 #define PCLK_PERI		230
171 #define PCLK_HDMI		231
172 #define PCLK_HDCP		232
173 #define PCLK_DCF		233
174 #define PCLK_SARADC		234
175 
176 /* hclk gates */
177 #define HCLK_PERI		308
178 #define HCLK_TSP		309
179 #define HCLK_GMAC		310
180 #define HCLK_I2S0_8CH		311
181 #define HCLK_I2S1_8CH		313
182 #define HCLK_I2S2_2CH		313
183 #define HCLK_SPDIF_8CH		314
184 #define HCLK_VOP		315
185 #define HCLK_NANDC		316
186 #define HCLK_SDMMC		317
187 #define HCLK_SDIO		318
188 #define HCLK_EMMC		319
189 #define HCLK_SDMMC_EXT		320
190 #define HCLK_RKVDEC_PRE		321
191 #define HCLK_RKVDEC		322
192 #define HCLK_RKVENC		323
193 #define HCLK_VPU_PRE		324
194 #define HCLK_VIO_PRE		325
195 #define HCLK_VPU		326
196 #define HCLK_VIO		327
197 #define HCLK_BUS_PRE		328
198 #define HCLK_PERI_PRE		329
199 #define HCLK_H264		330
200 #define HCLK_CIF		331
201 #define HCLK_OTG_PMU		332
202 #define HCLK_OTG		333
203 #define HCLK_HOST0		334
204 #define HCLK_HOST0_ARB		335
205 #define HCLK_CRYPTO_MST		336
206 #define HCLK_CRYPTO_SLV		337
207 #define HCLK_PDM		338
208 #define HCLK_IEP		339
209 #define HCLK_RGA		340
210 #define HCLK_HDCP		341
211 
212 #define CLK_NR_CLKS		(HCLK_HDCP + 1)
213 
214 /* soft-reset indices */
215 #define SRST_CORE0_PO		0
216 #define SRST_CORE1_PO		1
217 #define SRST_CORE2_PO		2
218 #define SRST_CORE3_PO		3
219 #define SRST_CORE0		4
220 #define SRST_CORE1		5
221 #define SRST_CORE2		6
222 #define SRST_CORE3		7
223 #define SRST_CORE0_DBG		8
224 #define SRST_CORE1_DBG		9
225 #define SRST_CORE2_DBG		10
226 #define SRST_CORE3_DBG		11
227 #define SRST_TOPDBG		12
228 #define SRST_CORE_NIU		13
229 #define SRST_STRC_A		14
230 #define SRST_L2C		15
231 
232 #define SRST_A53_GIC		18
233 #define SRST_DAP		19
234 #define SRST_PMU_P		21
235 #define SRST_EFUSE		22
236 #define SRST_BUSSYS_H		23
237 #define SRST_BUSSYS_P		24
238 #define SRST_SPDIF		25
239 #define SRST_INTMEM		26
240 #define SRST_ROM		27
241 #define SRST_GPIO0		28
242 #define SRST_GPIO1		29
243 #define SRST_GPIO2		30
244 #define SRST_GPIO3		31
245 
246 #define SRST_I2S0		32
247 #define SRST_I2S1		33
248 #define SRST_I2S2		34
249 #define SRST_I2S0_H		35
250 #define SRST_I2S1_H		36
251 #define SRST_I2S2_H		37
252 #define SRST_UART0		38
253 #define SRST_UART1		39
254 #define SRST_UART2		40
255 #define SRST_UART0_P		41
256 #define SRST_UART1_P		42
257 #define SRST_UART2_P		43
258 #define SRST_I2C0		44
259 #define SRST_I2C1		45
260 #define SRST_I2C2		46
261 #define SRST_I2C3		47
262 
263 #define SRST_I2C0_P		48
264 #define SRST_I2C1_P		49
265 #define SRST_I2C2_P		50
266 #define SRST_I2C3_P		51
267 #define SRST_EFUSE_SE_P		52
268 #define SRST_EFUSE_NS_P		53
269 #define SRST_PWM0		54
270 #define SRST_PWM0_P		55
271 #define SRST_DMA		56
272 #define SRST_TSP_A		57
273 #define SRST_TSP_H		58
274 #define SRST_TSP		59
275 #define SRST_TSP_HSADC		60
276 #define SRST_DCF_A		61
277 #define SRST_DCF_P		62
278 
279 #define SRST_SCR		64
280 #define SRST_SPI		65
281 #define SRST_TSADC		66
282 #define SRST_TSADC_P		67
283 #define SRST_CRYPTO		68
284 #define SRST_SGRF		69
285 #define SRST_GRF		70
286 #define SRST_USB_GRF		71
287 #define SRST_TIMER_6CH_P	72
288 #define SRST_TIMER0		73
289 #define SRST_TIMER1		74
290 #define SRST_TIMER2		75
291 #define SRST_TIMER3		76
292 #define SRST_TIMER4		77
293 #define SRST_TIMER5		78
294 #define SRST_USB3GRF		79
295 
296 #define SRST_PHYNIU		80
297 #define SRST_HDMIPHY		81
298 #define SRST_VDAC		82
299 #define SRST_ACODEC_p		83
300 #define SRST_SARADC		85
301 #define SRST_SARADC_P		86
302 #define SRST_GRF_DDR		87
303 #define SRST_DFIMON		88
304 #define SRST_MSCH		89
305 #define SRST_DDRMSCH		91
306 #define SRST_DDRCTRL		92
307 #define SRST_DDRCTRL_P		93
308 #define SRST_DDRPHY		94
309 #define SRST_DDRPHY_P		95
310 
311 #define SRST_GMAC_NIU_A		96
312 #define SRST_GMAC_NIU_P		97
313 #define SRST_GMAC2PHY_A		98
314 #define SRST_GMAC2IO_A		99
315 #define SRST_MACPHY		100
316 #define SRST_OTP_PHY		101
317 #define SRST_GPU_A		102
318 #define SRST_GPU_NIU_A		103
319 #define SRST_SDMMCEXT		104
320 #define SRST_PERIPH_NIU_A	105
321 #define SRST_PERIHP_NIU_H	106
322 #define SRST_PERIHP_P		107
323 #define SRST_PERIPHSYS_H	108
324 #define SRST_MMC0		109
325 #define SRST_SDIO		110
326 #define SRST_EMMC		111
327 
328 #define SRST_USB2OTG_H		112
329 #define SRST_USB2OTG		113
330 #define SRST_USB2OTG_ADP	114
331 #define SRST_USB2HOST_H		115
332 #define SRST_USB2HOST_ARB	116
333 #define SRST_USB2HOST_AUX	117
334 #define SRST_USB2HOST_EHCIPHY	118
335 #define SRST_USB2HOST_UTMI	119
336 #define SRST_USB3OTG		120
337 #define SRST_USBPOR		121
338 #define SRST_USB2OTG_UTMI	122
339 #define SRST_USB2HOST_PHY_UTMI	123
340 #define SRST_USB3OTG_UTMI	124
341 #define SRST_USB3PHY_U2		125
342 #define SRST_USB3PHY_U3		126
343 #define SRST_USB3PHY_PIPE	127
344 
345 #define SRST_VIO_A		128
346 #define SRST_VIO_BUS_H		129
347 #define SRST_VIO_H2P_H		130
348 #define SRST_VIO_ARBI_H		131
349 #define SRST_VOP_NIU_A		132
350 #define SRST_VOP_A		133
351 #define SRST_VOP_H		134
352 #define SRST_VOP_D		135
353 #define SRST_RGA		136
354 #define SRST_RGA_NIU_A		137
355 #define SRST_RGA_A		138
356 #define SRST_RGA_H		139
357 #define SRST_IEP_A		140
358 #define SRST_IEP_H		141
359 #define SRST_HDMI		142
360 #define SRST_HDMI_P		143
361 
362 #define SRST_HDCP_A		144
363 #define SRST_HDCP		145
364 #define SRST_HDCP_H		146
365 #define SRST_CIF_A		147
366 #define SRST_CIF_H		148
367 #define SRST_CIF_P		149
368 #define SRST_OTP_P		150
369 #define SRST_OTP_SBPI		151
370 #define SRST_OTP_USER		152
371 #define SRST_DDRCTRL_A		153
372 #define SRST_DDRSTDY_P		154
373 #define SRST_DDRSTDY		155
374 #define SRST_PDM_H		156
375 #define SRST_PDM		157
376 #define SRST_USB3PHY_OTG_P	158
377 #define SRST_USB3PHY_PIPE_P	159
378 
379 #define SRST_VCODEC_A		160
380 #define SRST_VCODEC_NIU_A	161
381 #define SRST_VCODEC_H		162
382 #define SRST_VCODEC_NIU_H	163
383 #define SRST_VDEC_A		164
384 #define SRST_VDEC_NIU_A		165
385 #define SRST_VDEC_H		166
386 #define SRST_VDEC_NIU_H		167
387 #define SRST_VDEC_CORE		168
388 #define SRST_VDEC_CABAC		169
389 #define SRST_DDRPHYDIV		175
390 
391 #define SRST_RKVENC_NIU_A	176
392 #define SRST_RKVENC_NIU_H	177
393 #define SRST_RKVENC_H265_A	178
394 #define SRST_RKVENC_H265_P	179
395 #define SRST_RKVENC_H265_CORE	180
396 #define SRST_RKVENC_H265_DSP	181
397 #define SRST_RKVENC_H264_A	182
398 #define SRST_RKVENC_H264_H	183
399 #define SRST_RKVENC_INTMEM	184
400 
401 #endif
402