1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 /* core clocks */ 17 #define PLL_APLL 1 18 #define PLL_DPLL 2 19 #define PLL_CPLL 3 20 #define PLL_GPLL 4 21 #define PLL_NPLL 5 22 #define ARMCLK 6 23 24 /* sclk gates (special clocks) */ 25 #define SCLK_GPU 64 26 #define SCLK_SPI0 65 27 #define SCLK_SPI1 66 28 #define SCLK_SPI2 67 29 #define SCLK_SDMMC 68 30 #define SCLK_SDIO0 69 31 #define SCLK_SDIO1 70 32 #define SCLK_EMMC 71 33 #define SCLK_TSADC 72 34 #define SCLK_SARADC 73 35 #define SCLK_PS2C 74 36 #define SCLK_NANDC0 75 37 #define SCLK_NANDC1 76 38 #define SCLK_UART0 77 39 #define SCLK_UART1 78 40 #define SCLK_UART2 79 41 #define SCLK_UART3 80 42 #define SCLK_UART4 81 43 #define SCLK_I2S0 82 44 #define SCLK_SPDIF 83 45 #define SCLK_SPDIF8CH 84 46 #define SCLK_TIMER0 85 47 #define SCLK_TIMER1 86 48 #define SCLK_TIMER2 87 49 #define SCLK_TIMER3 88 50 #define SCLK_TIMER4 89 51 #define SCLK_TIMER5 90 52 #define SCLK_TIMER6 91 53 #define SCLK_HSADC 92 54 #define SCLK_OTGPHY0 93 55 #define SCLK_OTGPHY1 94 56 #define SCLK_OTGPHY2 95 57 #define SCLK_OTG_ADP 96 58 #define SCLK_HSICPHY480M 97 59 #define SCLK_HSICPHY12M 98 60 #define SCLK_MACREF 99 61 #define SCLK_LCDC_PWM0 100 62 #define SCLK_LCDC_PWM1 101 63 #define SCLK_MAC_RX 102 64 #define SCLK_MAC_TX 103 65 #define SCLK_EDP_24M 104 66 #define SCLK_EDP 105 67 #define SCLK_RGA 106 68 #define SCLK_ISP 107 69 #define SCLK_ISP_JPE 108 70 #define SCLK_HDMI_HDCP 109 71 #define SCLK_HDMI_CEC 110 72 #define SCLK_HEVC_CABAC 111 73 #define SCLK_HEVC_CORE 112 74 #define SCLK_I2S0_OUT 113 75 #define SCLK_SDMMC_DRV 114 76 #define SCLK_SDIO0_DRV 115 77 #define SCLK_SDIO1_DRV 116 78 #define SCLK_EMMC_DRV 117 79 #define SCLK_SDMMC_SAMPLE 118 80 #define SCLK_SDIO0_SAMPLE 119 81 #define SCLK_SDIO1_SAMPLE 120 82 #define SCLK_EMMC_SAMPLE 121 83 84 #define DCLK_VOP0 190 85 #define DCLK_VOP1 191 86 87 /* aclk gates */ 88 #define ACLK_GPU 192 89 #define ACLK_DMAC1 193 90 #define ACLK_DMAC2 194 91 #define ACLK_MMU 195 92 #define ACLK_GMAC 196 93 #define ACLK_VOP0 197 94 #define ACLK_VOP1 198 95 #define ACLK_CRYPTO 199 96 #define ACLK_RGA 200 97 #define ACLK_RGA_NIU 201 98 #define ACLK_IEP 202 99 #define ACLK_VIO0_NIU 203 100 #define ACLK_VIP 204 101 #define ACLK_ISP 205 102 #define ACLK_VIO1_NIU 206 103 #define ACLK_HEVC 207 104 #define ACLK_VCODEC 208 105 #define ACLK_CPU 209 106 #define ACLK_PERI 210 107 108 /* pclk gates */ 109 #define PCLK_GPIO0 320 110 #define PCLK_GPIO1 321 111 #define PCLK_GPIO2 322 112 #define PCLK_GPIO3 323 113 #define PCLK_GPIO4 324 114 #define PCLK_GPIO5 325 115 #define PCLK_GPIO6 326 116 #define PCLK_GPIO7 327 117 #define PCLK_GPIO8 328 118 #define PCLK_GRF 329 119 #define PCLK_SGRF 330 120 #define PCLK_PMU 331 121 #define PCLK_I2C0 332 122 #define PCLK_I2C1 333 123 #define PCLK_I2C2 334 124 #define PCLK_I2C3 335 125 #define PCLK_I2C4 336 126 #define PCLK_I2C5 337 127 #define PCLK_SPI0 338 128 #define PCLK_SPI1 339 129 #define PCLK_SPI2 340 130 #define PCLK_UART0 341 131 #define PCLK_UART1 342 132 #define PCLK_UART2 343 133 #define PCLK_UART3 344 134 #define PCLK_UART4 345 135 #define PCLK_TSADC 346 136 #define PCLK_SARADC 347 137 #define PCLK_SIM 348 138 #define PCLK_GMAC 349 139 #define PCLK_PWM 350 140 #define PCLK_RKPWM 351 141 #define PCLK_PS2C 352 142 #define PCLK_TIMER 353 143 #define PCLK_TZPC 354 144 #define PCLK_EDP_CTRL 355 145 #define PCLK_MIPI_DSI0 356 146 #define PCLK_MIPI_DSI1 357 147 #define PCLK_MIPI_CSI 358 148 #define PCLK_LVDS_PHY 359 149 #define PCLK_HDMI_CTRL 360 150 #define PCLK_VIO2_H2P 361 151 #define PCLK_CPU 362 152 #define PCLK_PERI 363 153 #define PCLK_DDRUPCTL0 364 154 #define PCLK_PUBL0 365 155 #define PCLK_DDRUPCTL1 366 156 #define PCLK_PUBL1 367 157 158 /* hclk gates */ 159 #define HCLK_GPS 448 160 #define HCLK_OTG0 449 161 #define HCLK_USBHOST0 450 162 #define HCLK_USBHOST1 451 163 #define HCLK_HSIC 452 164 #define HCLK_NANDC0 453 165 #define HCLK_NANDC1 454 166 #define HCLK_TSP 455 167 #define HCLK_SDMMC 456 168 #define HCLK_SDIO0 457 169 #define HCLK_SDIO1 458 170 #define HCLK_EMMC 459 171 #define HCLK_HSADC 460 172 #define HCLK_CRYPTO 461 173 #define HCLK_I2S0 462 174 #define HCLK_SPDIF 463 175 #define HCLK_SPDIF8CH 464 176 #define HCLK_VOP0 465 177 #define HCLK_VOP1 466 178 #define HCLK_ROM 467 179 #define HCLK_IEP 468 180 #define HCLK_ISP 469 181 #define HCLK_RGA 470 182 #define HCLK_VIO_AHB_ARBI 471 183 #define HCLK_VIO_NIU 472 184 #define HCLK_VIP 473 185 #define HCLK_VIO2_H2P 474 186 #define HCLK_HEVC 475 187 #define HCLK_VCODEC 476 188 #define HCLK_CPU 477 189 #define HCLK_PERI 478 190 191 #define CLK_NR_CLKS (HCLK_PERI + 1) 192 193 /* soft-reset indices */ 194 #define SRST_CORE0 0 195 #define SRST_CORE1 1 196 #define SRST_CORE2 2 197 #define SRST_CORE3 3 198 #define SRST_CORE0_PO 4 199 #define SRST_CORE1_PO 5 200 #define SRST_CORE2_PO 6 201 #define SRST_CORE3_PO 7 202 #define SRST_PDCORE_STRSYS 8 203 #define SRST_PDBUS_STRSYS 9 204 #define SRST_L2C 10 205 #define SRST_TOPDBG 11 206 #define SRST_CORE0_DBG 12 207 #define SRST_CORE1_DBG 13 208 #define SRST_CORE2_DBG 14 209 #define SRST_CORE3_DBG 15 210 211 #define SRST_PDBUG_AHB_ARBITOR 16 212 #define SRST_EFUSE256 17 213 #define SRST_DMAC1 18 214 #define SRST_INTMEM 19 215 #define SRST_ROM 20 216 #define SRST_SPDIF8CH 21 217 #define SRST_TIMER 22 218 #define SRST_I2S0 23 219 #define SRST_SPDIF 24 220 #define SRST_TIMER0 25 221 #define SRST_TIMER1 26 222 #define SRST_TIMER2 27 223 #define SRST_TIMER3 28 224 #define SRST_TIMER4 29 225 #define SRST_TIMER5 30 226 #define SRST_EFUSE 31 227 228 #define SRST_GPIO0 32 229 #define SRST_GPIO1 33 230 #define SRST_GPIO2 34 231 #define SRST_GPIO3 35 232 #define SRST_GPIO4 36 233 #define SRST_GPIO5 37 234 #define SRST_GPIO6 38 235 #define SRST_GPIO7 39 236 #define SRST_GPIO8 40 237 #define SRST_I2C0 42 238 #define SRST_I2C1 43 239 #define SRST_I2C2 44 240 #define SRST_I2C3 45 241 #define SRST_I2C4 46 242 #define SRST_I2C5 47 243 244 #define SRST_DWPWM 48 245 #define SRST_MMC_PERI 49 246 #define SRST_PERIPH_MMU 50 247 #define SRST_DAP 51 248 #define SRST_DAP_SYS 52 249 #define SRST_TPIU 53 250 #define SRST_PMU_APB 54 251 #define SRST_GRF 55 252 #define SRST_PMU 56 253 #define SRST_PERIPH_AXI 57 254 #define SRST_PERIPH_AHB 58 255 #define SRST_PERIPH_APB 59 256 #define SRST_PERIPH_NIU 60 257 #define SRST_PDPERI_AHB_ARBI 61 258 #define SRST_EMEM 62 259 #define SRST_USB_PERI 63 260 261 #define SRST_DMAC2 64 262 #define SRST_MAC 66 263 #define SRST_GPS 67 264 #define SRST_RKPWM 69 265 #define SRST_CCP 71 266 #define SRST_USBHOST0 72 267 #define SRST_HSIC 73 268 #define SRST_HSIC_AUX 74 269 #define SRST_HSIC_PHY 75 270 #define SRST_HSADC 76 271 #define SRST_NANDC0 77 272 #define SRST_NANDC1 78 273 274 #define SRST_TZPC 80 275 #define SRST_SPI0 83 276 #define SRST_SPI1 84 277 #define SRST_SPI2 85 278 #define SRST_SARADC 87 279 #define SRST_PDALIVE_NIU 88 280 #define SRST_PDPMU_INTMEM 89 281 #define SRST_PDPMU_NIU 90 282 #define SRST_SGRF 91 283 284 #define SRST_VIO_ARBI 96 285 #define SRST_RGA_NIU 97 286 #define SRST_VIO0_NIU_AXI 98 287 #define SRST_VIO_NIU_AHB 99 288 #define SRST_LCDC0_AXI 100 289 #define SRST_LCDC0_AHB 101 290 #define SRST_LCDC0_DCLK 102 291 #define SRST_VIO1_NIU_AXI 103 292 #define SRST_VIP 104 293 #define SRST_RGA_CORE 105 294 #define SRST_IEP_AXI 106 295 #define SRST_IEP_AHB 107 296 #define SRST_RGA_AXI 108 297 #define SRST_RGA_AHB 109 298 #define SRST_ISP 110 299 #define SRST_EDP 111 300 301 #define SRST_VCODEC_AXI 112 302 #define SRST_VCODEC_AHB 113 303 #define SRST_VIO_H2P 114 304 #define SRST_MIPIDSI0 115 305 #define SRST_MIPIDSI1 116 306 #define SRST_MIPICSI 117 307 #define SRST_LVDS_PHY 118 308 #define SRST_LVDS_CON 119 309 #define SRST_GPU 120 310 #define SRST_HDMI 121 311 #define SRST_CORE_PVTM 124 312 #define SRST_GPU_PVTM 125 313 314 #define SRST_MMC0 128 315 #define SRST_SDIO0 129 316 #define SRST_SDIO1 130 317 #define SRST_EMMC 131 318 #define SRST_USBOTG_AHB 132 319 #define SRST_USBOTG_PHY 133 320 #define SRST_USBOTG_CON 134 321 #define SRST_USBHOST0_AHB 135 322 #define SRST_USBHOST0_PHY 136 323 #define SRST_USBHOST0_CON 137 324 #define SRST_USBHOST1_AHB 138 325 #define SRST_USBHOST1_PHY 139 326 #define SRST_USBHOST1_CON 140 327 #define SRST_USB_ADP 141 328 #define SRST_ACC_EFUSE 142 329 330 #define SRST_CORESIGHT 144 331 #define SRST_PD_CORE_AHB_NOC 145 332 #define SRST_PD_CORE_APB_NOC 146 333 #define SRST_PD_CORE_MP_AXI 147 334 #define SRST_GIC 148 335 #define SRST_LCDC_PWM0 149 336 #define SRST_LCDC_PWM1 150 337 #define SRST_VIO0_H2P_BRG 151 338 #define SRST_VIO1_H2P_BRG 152 339 #define SRST_RGA_H2P_BRG 153 340 #define SRST_HEVC 154 341 #define SRST_TSADC 159 342 343 #define SRST_DDRPHY0 160 344 #define SRST_DDRPHY0_APB 161 345 #define SRST_DDRCTRL0 162 346 #define SRST_DDRCTRL0_APB 163 347 #define SRST_DDRPHY0_CTRL 164 348 #define SRST_DDRPHY1 165 349 #define SRST_DDRPHY1_APB 166 350 #define SRST_DDRCTRL1 167 351 #define SRST_DDRCTRL1_APB 168 352 #define SRST_DDRPHY1_CTRL 169 353 #define SRST_DDRMSCH0 170 354 #define SRST_DDRMSCH1 171 355 #define SRST_CRYPTO 174 356 #define SRST_C2C_HOST 175 357 358 #define SRST_LCDC1_AXI 176 359 #define SRST_LCDC1_AHB 177 360 #define SRST_LCDC1_DCLK 178 361 #define SRST_UART0 179 362 #define SRST_UART1 180 363 #define SRST_UART2 181 364 #define SRST_UART3 182 365 #define SRST_UART4 183 366 #define SRST_SIMC 186 367 #define SRST_PS2C 187 368 #define SRST_TSP 188 369 #define SRST_TSP_CLKIN0 189 370 #define SRST_TSP_CLKIN1 190 371 #define SRST_TSP_27M 191 372