1 /* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 18 19 /* core clocks */ 20 #define PLL_APLL 1 21 #define PLL_DPLL 2 22 #define PLL_CPLL 3 23 #define PLL_GPLL 4 24 #define PLL_NPLL 5 25 #define ARMCLK 6 26 27 /* sclk gates (special clocks) */ 28 #define SCLK_GPU 64 29 #define SCLK_SPI0 65 30 #define SCLK_SPI1 66 31 #define SCLK_SPI2 67 32 #define SCLK_SDMMC 68 33 #define SCLK_SDIO0 69 34 #define SCLK_SDIO1 70 35 #define SCLK_EMMC 71 36 #define SCLK_TSADC 72 37 #define SCLK_SARADC 73 38 #define SCLK_PS2C 74 39 #define SCLK_NANDC0 75 40 #define SCLK_NANDC1 76 41 #define SCLK_UART0 77 42 #define SCLK_UART1 78 43 #define SCLK_UART2 79 44 #define SCLK_UART3 80 45 #define SCLK_UART4 81 46 #define SCLK_I2S0 82 47 #define SCLK_SPDIF 83 48 #define SCLK_SPDIF8CH 84 49 #define SCLK_TIMER0 85 50 #define SCLK_TIMER1 86 51 #define SCLK_TIMER2 87 52 #define SCLK_TIMER3 88 53 #define SCLK_TIMER4 89 54 #define SCLK_TIMER5 90 55 #define SCLK_TIMER6 91 56 #define SCLK_HSADC 92 57 #define SCLK_OTGPHY0 93 58 #define SCLK_OTGPHY1 94 59 #define SCLK_OTGPHY2 95 60 #define SCLK_OTG_ADP 96 61 #define SCLK_HSICPHY480M 97 62 #define SCLK_HSICPHY12M 98 63 #define SCLK_MACREF 99 64 #define SCLK_LCDC_PWM0 100 65 #define SCLK_LCDC_PWM1 101 66 #define SCLK_MAC_RX 102 67 #define SCLK_MAC_TX 103 68 #define SCLK_EDP_24M 104 69 #define SCLK_EDP 105 70 #define SCLK_RGA 106 71 #define SCLK_ISP 107 72 #define SCLK_ISP_JPE 108 73 #define SCLK_HDMI_HDCP 109 74 #define SCLK_HDMI_CEC 110 75 #define SCLK_HEVC_CABAC 111 76 #define SCLK_HEVC_CORE 112 77 #define SCLK_I2S0_OUT 113 78 #define SCLK_SDMMC_DRV 114 79 #define SCLK_SDIO0_DRV 115 80 #define SCLK_SDIO1_DRV 116 81 #define SCLK_EMMC_DRV 117 82 #define SCLK_SDMMC_SAMPLE 118 83 #define SCLK_SDIO0_SAMPLE 119 84 #define SCLK_SDIO1_SAMPLE 120 85 #define SCLK_EMMC_SAMPLE 121 86 #define SCLK_USBPHY480M_SRC 122 87 #define SCLK_PVTM_CORE 123 88 #define SCLK_PVTM_GPU 124 89 90 #define SCLK_MAC 151 91 #define SCLK_MACREF_OUT 152 92 93 #define DCLK_VOP0 190 94 #define DCLK_VOP1 191 95 96 /* aclk gates */ 97 #define ACLK_GPU 192 98 #define ACLK_DMAC1 193 99 #define ACLK_DMAC2 194 100 #define ACLK_MMU 195 101 #define ACLK_GMAC 196 102 #define ACLK_VOP0 197 103 #define ACLK_VOP1 198 104 #define ACLK_CRYPTO 199 105 #define ACLK_RGA 200 106 #define ACLK_RGA_NIU 201 107 #define ACLK_IEP 202 108 #define ACLK_VIO0_NIU 203 109 #define ACLK_VIP 204 110 #define ACLK_ISP 205 111 #define ACLK_VIO1_NIU 206 112 #define ACLK_HEVC 207 113 #define ACLK_VCODEC 208 114 #define ACLK_CPU 209 115 #define ACLK_PERI 210 116 117 /* pclk gates */ 118 #define PCLK_GPIO0 320 119 #define PCLK_GPIO1 321 120 #define PCLK_GPIO2 322 121 #define PCLK_GPIO3 323 122 #define PCLK_GPIO4 324 123 #define PCLK_GPIO5 325 124 #define PCLK_GPIO6 326 125 #define PCLK_GPIO7 327 126 #define PCLK_GPIO8 328 127 #define PCLK_GRF 329 128 #define PCLK_SGRF 330 129 #define PCLK_PMU 331 130 #define PCLK_I2C0 332 131 #define PCLK_I2C1 333 132 #define PCLK_I2C2 334 133 #define PCLK_I2C3 335 134 #define PCLK_I2C4 336 135 #define PCLK_I2C5 337 136 #define PCLK_SPI0 338 137 #define PCLK_SPI1 339 138 #define PCLK_SPI2 340 139 #define PCLK_UART0 341 140 #define PCLK_UART1 342 141 #define PCLK_UART2 343 142 #define PCLK_UART3 344 143 #define PCLK_UART4 345 144 #define PCLK_TSADC 346 145 #define PCLK_SARADC 347 146 #define PCLK_SIM 348 147 #define PCLK_GMAC 349 148 #define PCLK_PWM 350 149 #define PCLK_RKPWM 351 150 #define PCLK_PS2C 352 151 #define PCLK_TIMER 353 152 #define PCLK_TZPC 354 153 #define PCLK_EDP_CTRL 355 154 #define PCLK_MIPI_DSI0 356 155 #define PCLK_MIPI_DSI1 357 156 #define PCLK_MIPI_CSI 358 157 #define PCLK_LVDS_PHY 359 158 #define PCLK_HDMI_CTRL 360 159 #define PCLK_VIO2_H2P 361 160 #define PCLK_CPU 362 161 #define PCLK_PERI 363 162 #define PCLK_DDRUPCTL0 364 163 #define PCLK_PUBL0 365 164 #define PCLK_DDRUPCTL1 366 165 #define PCLK_PUBL1 367 166 #define PCLK_WDT 368 167 168 /* hclk gates */ 169 #define HCLK_GPS 448 170 #define HCLK_OTG0 449 171 #define HCLK_USBHOST0 450 172 #define HCLK_USBHOST1 451 173 #define HCLK_HSIC 452 174 #define HCLK_NANDC0 453 175 #define HCLK_NANDC1 454 176 #define HCLK_TSP 455 177 #define HCLK_SDMMC 456 178 #define HCLK_SDIO0 457 179 #define HCLK_SDIO1 458 180 #define HCLK_EMMC 459 181 #define HCLK_HSADC 460 182 #define HCLK_CRYPTO 461 183 #define HCLK_I2S0 462 184 #define HCLK_SPDIF 463 185 #define HCLK_SPDIF8CH 464 186 #define HCLK_VOP0 465 187 #define HCLK_VOP1 466 188 #define HCLK_ROM 467 189 #define HCLK_IEP 468 190 #define HCLK_ISP 469 191 #define HCLK_RGA 470 192 #define HCLK_VIO_AHB_ARBI 471 193 #define HCLK_VIO_NIU 472 194 #define HCLK_VIP 473 195 #define HCLK_VIO2_H2P 474 196 #define HCLK_HEVC 475 197 #define HCLK_VCODEC 476 198 #define HCLK_CPU 477 199 #define HCLK_PERI 478 200 201 #define CLK_NR_CLKS (HCLK_PERI + 1) 202 203 /* soft-reset indices */ 204 #define SRST_CORE0 0 205 #define SRST_CORE1 1 206 #define SRST_CORE2 2 207 #define SRST_CORE3 3 208 #define SRST_CORE0_PO 4 209 #define SRST_CORE1_PO 5 210 #define SRST_CORE2_PO 6 211 #define SRST_CORE3_PO 7 212 #define SRST_PDCORE_STRSYS 8 213 #define SRST_PDBUS_STRSYS 9 214 #define SRST_L2C 10 215 #define SRST_TOPDBG 11 216 #define SRST_CORE0_DBG 12 217 #define SRST_CORE1_DBG 13 218 #define SRST_CORE2_DBG 14 219 #define SRST_CORE3_DBG 15 220 221 #define SRST_PDBUG_AHB_ARBITOR 16 222 #define SRST_EFUSE256 17 223 #define SRST_DMAC1 18 224 #define SRST_INTMEM 19 225 #define SRST_ROM 20 226 #define SRST_SPDIF8CH 21 227 #define SRST_TIMER 22 228 #define SRST_I2S0 23 229 #define SRST_SPDIF 24 230 #define SRST_TIMER0 25 231 #define SRST_TIMER1 26 232 #define SRST_TIMER2 27 233 #define SRST_TIMER3 28 234 #define SRST_TIMER4 29 235 #define SRST_TIMER5 30 236 #define SRST_EFUSE 31 237 238 #define SRST_GPIO0 32 239 #define SRST_GPIO1 33 240 #define SRST_GPIO2 34 241 #define SRST_GPIO3 35 242 #define SRST_GPIO4 36 243 #define SRST_GPIO5 37 244 #define SRST_GPIO6 38 245 #define SRST_GPIO7 39 246 #define SRST_GPIO8 40 247 #define SRST_I2C0 42 248 #define SRST_I2C1 43 249 #define SRST_I2C2 44 250 #define SRST_I2C3 45 251 #define SRST_I2C4 46 252 #define SRST_I2C5 47 253 254 #define SRST_DWPWM 48 255 #define SRST_MMC_PERI 49 256 #define SRST_PERIPH_MMU 50 257 #define SRST_DAP 51 258 #define SRST_DAP_SYS 52 259 #define SRST_TPIU 53 260 #define SRST_PMU_APB 54 261 #define SRST_GRF 55 262 #define SRST_PMU 56 263 #define SRST_PERIPH_AXI 57 264 #define SRST_PERIPH_AHB 58 265 #define SRST_PERIPH_APB 59 266 #define SRST_PERIPH_NIU 60 267 #define SRST_PDPERI_AHB_ARBI 61 268 #define SRST_EMEM 62 269 #define SRST_USB_PERI 63 270 271 #define SRST_DMAC2 64 272 #define SRST_MAC 66 273 #define SRST_GPS 67 274 #define SRST_RKPWM 69 275 #define SRST_CCP 71 276 #define SRST_USBHOST0 72 277 #define SRST_HSIC 73 278 #define SRST_HSIC_AUX 74 279 #define SRST_HSIC_PHY 75 280 #define SRST_HSADC 76 281 #define SRST_NANDC0 77 282 #define SRST_NANDC1 78 283 284 #define SRST_TZPC 80 285 #define SRST_SPI0 83 286 #define SRST_SPI1 84 287 #define SRST_SPI2 85 288 #define SRST_SARADC 87 289 #define SRST_PDALIVE_NIU 88 290 #define SRST_PDPMU_INTMEM 89 291 #define SRST_PDPMU_NIU 90 292 #define SRST_SGRF 91 293 294 #define SRST_VIO_ARBI 96 295 #define SRST_RGA_NIU 97 296 #define SRST_VIO0_NIU_AXI 98 297 #define SRST_VIO_NIU_AHB 99 298 #define SRST_LCDC0_AXI 100 299 #define SRST_LCDC0_AHB 101 300 #define SRST_LCDC0_DCLK 102 301 #define SRST_VIO1_NIU_AXI 103 302 #define SRST_VIP 104 303 #define SRST_RGA_CORE 105 304 #define SRST_IEP_AXI 106 305 #define SRST_IEP_AHB 107 306 #define SRST_RGA_AXI 108 307 #define SRST_RGA_AHB 109 308 #define SRST_ISP 110 309 #define SRST_EDP 111 310 311 #define SRST_VCODEC_AXI 112 312 #define SRST_VCODEC_AHB 113 313 #define SRST_VIO_H2P 114 314 #define SRST_MIPIDSI0 115 315 #define SRST_MIPIDSI1 116 316 #define SRST_MIPICSI 117 317 #define SRST_LVDS_PHY 118 318 #define SRST_LVDS_CON 119 319 #define SRST_GPU 120 320 #define SRST_HDMI 121 321 #define SRST_CORE_PVTM 124 322 #define SRST_GPU_PVTM 125 323 324 #define SRST_MMC0 128 325 #define SRST_SDIO0 129 326 #define SRST_SDIO1 130 327 #define SRST_EMMC 131 328 #define SRST_USBOTG_AHB 132 329 #define SRST_USBOTG_PHY 133 330 #define SRST_USBOTG_CON 134 331 #define SRST_USBHOST0_AHB 135 332 #define SRST_USBHOST0_PHY 136 333 #define SRST_USBHOST0_CON 137 334 #define SRST_USBHOST1_AHB 138 335 #define SRST_USBHOST1_PHY 139 336 #define SRST_USBHOST1_CON 140 337 #define SRST_USB_ADP 141 338 #define SRST_ACC_EFUSE 142 339 340 #define SRST_CORESIGHT 144 341 #define SRST_PD_CORE_AHB_NOC 145 342 #define SRST_PD_CORE_APB_NOC 146 343 #define SRST_PD_CORE_MP_AXI 147 344 #define SRST_GIC 148 345 #define SRST_LCDC_PWM0 149 346 #define SRST_LCDC_PWM1 150 347 #define SRST_VIO0_H2P_BRG 151 348 #define SRST_VIO1_H2P_BRG 152 349 #define SRST_RGA_H2P_BRG 153 350 #define SRST_HEVC 154 351 #define SRST_TSADC 159 352 353 #define SRST_DDRPHY0 160 354 #define SRST_DDRPHY0_APB 161 355 #define SRST_DDRCTRL0 162 356 #define SRST_DDRCTRL0_APB 163 357 #define SRST_DDRPHY0_CTRL 164 358 #define SRST_DDRPHY1 165 359 #define SRST_DDRPHY1_APB 166 360 #define SRST_DDRCTRL1 167 361 #define SRST_DDRCTRL1_APB 168 362 #define SRST_DDRPHY1_CTRL 169 363 #define SRST_DDRMSCH0 170 364 #define SRST_DDRMSCH1 171 365 #define SRST_CRYPTO 174 366 #define SRST_C2C_HOST 175 367 368 #define SRST_LCDC1_AXI 176 369 #define SRST_LCDC1_AHB 177 370 #define SRST_LCDC1_DCLK 178 371 #define SRST_UART0 179 372 #define SRST_UART1 180 373 #define SRST_UART2 181 374 #define SRST_UART3 182 375 #define SRST_UART4 183 376 #define SRST_SIMC 186 377 #define SRST_PS2C 187 378 #define SRST_TSP 188 379 #define SRST_TSP_CLKIN0 189 380 #define SRST_TSP_CLKIN1 190 381 #define SRST_TSP_27M 191 382 383 #endif 384