1 /* 2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 18 19 /* core clocks */ 20 #define PLL_APLL 1 21 #define PLL_DPLL 2 22 #define PLL_CPLL 3 23 #define PLL_GPLL 4 24 #define ARMCLK 5 25 26 /* sclk gates (special clocks) */ 27 #define SCLK_SPI0 65 28 #define SCLK_NANDC 67 29 #define SCLK_SDMMC 68 30 #define SCLK_SDIO 69 31 #define SCLK_EMMC 71 32 #define SCLK_UART0 77 33 #define SCLK_UART1 78 34 #define SCLK_UART2 79 35 #define SCLK_I2S0 80 36 #define SCLK_I2S1 81 37 #define SCLK_I2S2 82 38 #define SCLK_SPDIF 83 39 #define SCLK_TIMER0 85 40 #define SCLK_TIMER1 86 41 #define SCLK_TIMER2 87 42 #define SCLK_TIMER3 88 43 #define SCLK_TIMER4 89 44 #define SCLK_TIMER5 90 45 #define SCLK_I2S_OUT 113 46 #define SCLK_SDMMC_DRV 114 47 #define SCLK_SDIO_DRV 115 48 #define SCLK_EMMC_DRV 117 49 #define SCLK_SDMMC_SAMPLE 118 50 #define SCLK_SDIO_SAMPLE 119 51 #define SCLK_EMMC_SAMPLE 121 52 53 /* aclk gates */ 54 #define ACLK_DMAC 194 55 #define ACLK_PERI 210 56 57 /* pclk gates */ 58 #define PCLK_GPIO0 320 59 #define PCLK_GPIO1 321 60 #define PCLK_GPIO2 322 61 #define PCLK_GPIO3 323 62 #define PCLK_GRF 329 63 #define PCLK_I2C0 332 64 #define PCLK_I2C1 333 65 #define PCLK_I2C2 334 66 #define PCLK_I2C3 335 67 #define PCLK_SPI0 338 68 #define PCLK_UART0 341 69 #define PCLK_UART1 342 70 #define PCLK_UART2 343 71 #define PCLK_PWM 350 72 #define PCLK_TIMER 353 73 #define PCLK_PERI 363 74 75 /* hclk gates */ 76 #define HCLK_NANDC 453 77 #define HCLK_SDMMC 456 78 #define HCLK_SDIO 457 79 #define HCLK_EMMC 459 80 #define HCLK_PERI 478 81 82 #define CLK_NR_CLKS (HCLK_PERI + 1) 83 84 /* soft-reset indices */ 85 #define SRST_CORE0_PO 0 86 #define SRST_CORE1_PO 1 87 #define SRST_CORE2_PO 2 88 #define SRST_CORE3_PO 3 89 #define SRST_CORE0 4 90 #define SRST_CORE1 5 91 #define SRST_CORE2 6 92 #define SRST_CORE3 7 93 #define SRST_CORE0_DBG 8 94 #define SRST_CORE1_DBG 9 95 #define SRST_CORE2_DBG 10 96 #define SRST_CORE3_DBG 11 97 #define SRST_TOPDBG 12 98 #define SRST_ACLK_CORE 13 99 #define SRST_NOC 14 100 #define SRST_L2C 15 101 102 #define SRST_CPUSYS_H 18 103 #define SRST_BUSSYS_H 19 104 #define SRST_SPDIF 20 105 #define SRST_INTMEM 21 106 #define SRST_ROM 22 107 #define SRST_OTG_ADP 23 108 #define SRST_I2S0 24 109 #define SRST_I2S1 25 110 #define SRST_I2S2 26 111 #define SRST_ACODEC_P 27 112 #define SRST_DFIMON 28 113 #define SRST_MSCH 29 114 #define SRST_EFUSE1024 30 115 #define SRST_EFUSE256 31 116 117 #define SRST_GPIO0 32 118 #define SRST_GPIO1 33 119 #define SRST_GPIO2 34 120 #define SRST_GPIO3 35 121 #define SRST_PERIPH_NOC_A 36 122 #define SRST_PERIPH_NOC_BUS_H 37 123 #define SRST_PERIPH_NOC_P 38 124 #define SRST_UART0 39 125 #define SRST_UART1 40 126 #define SRST_UART2 41 127 #define SRST_PHYNOC 42 128 #define SRST_I2C0 43 129 #define SRST_I2C1 44 130 #define SRST_I2C2 45 131 #define SRST_I2C3 46 132 133 #define SRST_PWM 48 134 #define SRST_A53_GIC 49 135 #define SRST_DAP 51 136 #define SRST_DAP_NOC 52 137 #define SRST_CRYPTO 53 138 #define SRST_SGRF 54 139 #define SRST_GRF 55 140 #define SRST_GMAC 56 141 #define SRST_PERIPH_NOC_H 58 142 #define SRST_MACPHY 63 143 144 #define SRST_DMA 64 145 #define SRST_NANDC 68 146 #define SRST_USBOTG 69 147 #define SRST_OTGC 70 148 #define SRST_USBHOST0 71 149 #define SRST_HOST_CTRL0 72 150 #define SRST_USBHOST1 73 151 #define SRST_HOST_CTRL1 74 152 #define SRST_USBHOST2 75 153 #define SRST_HOST_CTRL2 76 154 #define SRST_USBPOR0 77 155 #define SRST_USBPOR1 78 156 #define SRST_DDRMSCH 79 157 158 #define SRST_SMART_CARD 80 159 #define SRST_SDMMC 81 160 #define SRST_SDIO 82 161 #define SRST_EMMC 83 162 #define SRST_SPI 84 163 #define SRST_TSP_H 85 164 #define SRST_TSP 86 165 #define SRST_TSADC 87 166 #define SRST_DDRPHY 88 167 #define SRST_DDRPHY_P 89 168 #define SRST_DDRCTRL 90 169 #define SRST_DDRCTRL_P 91 170 #define SRST_HOST0_ECHI 92 171 #define SRST_HOST1_ECHI 93 172 #define SRST_HOST2_ECHI 94 173 #define SRST_VOP_NOC_A 95 174 175 #define SRST_HDMI_P 96 176 #define SRST_VIO_ARBI_H 97 177 #define SRST_IEP_NOC_A 98 178 #define SRST_VIO_NOC_H 99 179 #define SRST_VOP_A 100 180 #define SRST_VOP_H 101 181 #define SRST_VOP_D 102 182 #define SRST_UTMI0 103 183 #define SRST_UTMI1 104 184 #define SRST_UTMI2 105 185 #define SRST_UTMI3 106 186 #define SRST_RGA 107 187 #define SRST_RGA_NOC_A 108 188 #define SRST_RGA_A 109 189 #define SRST_RGA_H 110 190 #define SRST_HDCP_A 111 191 192 #define SRST_VPU_A 112 193 #define SRST_VPU_H 113 194 #define SRST_VPU_NOC_A 116 195 #define SRST_VPU_NOC_H 117 196 #define SRST_RKVDEC_A 118 197 #define SRST_RKVDEC_NOC_A 119 198 #define SRST_RKVDEC_H 120 199 #define SRST_RKVDEC_NOC_H 121 200 #define SRST_RKVDEC_CORE 122 201 #define SRST_RKVDEC_CABAC 123 202 #define SRST_IEP_A 124 203 #define SRST_IEP_H 125 204 #define SRST_GPU_A 126 205 #define SRST_GPU_NOC_A 127 206 207 #define SRST_CORE_DBG 128 208 #define SRST_DBG_P 129 209 #define SRST_TIMER0 130 210 #define SRST_TIMER1 131 211 #define SRST_TIMER2 132 212 #define SRST_TIMER3 133 213 #define SRST_TIMER4 134 214 #define SRST_TIMER5 135 215 #define SRST_VIO_H2P 136 216 #define SRST_HDMIPHY 139 217 #define SRST_VDAC 140 218 #define SRST_TIMER_6CH_P 141 219 220 #endif 221