1*40392137SLad Prabhakar /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*40392137SLad Prabhakar * 3*40392137SLad Prabhakar * Copyright (C) 2021 Renesas Electronics Corp. 4*40392137SLad Prabhakar */ 5*40392137SLad Prabhakar #ifndef __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ 6*40392137SLad Prabhakar #define __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ 7*40392137SLad Prabhakar 8*40392137SLad Prabhakar #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*40392137SLad Prabhakar 10*40392137SLad Prabhakar /* R9A07G044 CPG Core Clocks */ 11*40392137SLad Prabhakar #define R9A07G044_CLK_I 0 12*40392137SLad Prabhakar #define R9A07G044_CLK_I2 1 13*40392137SLad Prabhakar #define R9A07G044_CLK_G 2 14*40392137SLad Prabhakar #define R9A07G044_CLK_S0 3 15*40392137SLad Prabhakar #define R9A07G044_CLK_S1 4 16*40392137SLad Prabhakar #define R9A07G044_CLK_SPI0 5 17*40392137SLad Prabhakar #define R9A07G044_CLK_SPI1 6 18*40392137SLad Prabhakar #define R9A07G044_CLK_SD0 7 19*40392137SLad Prabhakar #define R9A07G044_CLK_SD1 8 20*40392137SLad Prabhakar #define R9A07G044_CLK_M0 9 21*40392137SLad Prabhakar #define R9A07G044_CLK_M1 10 22*40392137SLad Prabhakar #define R9A07G044_CLK_M2 11 23*40392137SLad Prabhakar #define R9A07G044_CLK_M3 12 24*40392137SLad Prabhakar #define R9A07G044_CLK_M4 13 25*40392137SLad Prabhakar #define R9A07G044_CLK_HP 14 26*40392137SLad Prabhakar #define R9A07G044_CLK_TSU 15 27*40392137SLad Prabhakar #define R9A07G044_CLK_ZT 16 28*40392137SLad Prabhakar #define R9A07G044_CLK_P0 17 29*40392137SLad Prabhakar #define R9A07G044_CLK_P1 18 30*40392137SLad Prabhakar #define R9A07G044_CLK_P2 19 31*40392137SLad Prabhakar #define R9A07G044_CLK_AT 20 32*40392137SLad Prabhakar #define R9A07G044_OSCCLK 21 33*40392137SLad Prabhakar 34*40392137SLad Prabhakar /* R9A07G044 Module Clocks */ 35*40392137SLad Prabhakar #define R9A07G044_CLK_GIC600 0 36*40392137SLad Prabhakar #define R9A07G044_CLK_IA55 1 37*40392137SLad Prabhakar #define R9A07G044_CLK_SYC 2 38*40392137SLad Prabhakar #define R9A07G044_CLK_DMAC 3 39*40392137SLad Prabhakar #define R9A07G044_CLK_SYSC 4 40*40392137SLad Prabhakar #define R9A07G044_CLK_MTU 5 41*40392137SLad Prabhakar #define R9A07G044_CLK_GPT 6 42*40392137SLad Prabhakar #define R9A07G044_CLK_ETH0 7 43*40392137SLad Prabhakar #define R9A07G044_CLK_ETH1 8 44*40392137SLad Prabhakar #define R9A07G044_CLK_I2C0 9 45*40392137SLad Prabhakar #define R9A07G044_CLK_I2C1 10 46*40392137SLad Prabhakar #define R9A07G044_CLK_I2C2 11 47*40392137SLad Prabhakar #define R9A07G044_CLK_I2C3 12 48*40392137SLad Prabhakar #define R9A07G044_CLK_SCIF0 13 49*40392137SLad Prabhakar #define R9A07G044_CLK_SCIF1 14 50*40392137SLad Prabhakar #define R9A07G044_CLK_SCIF2 15 51*40392137SLad Prabhakar #define R9A07G044_CLK_SCIF3 16 52*40392137SLad Prabhakar #define R9A07G044_CLK_SCIF4 17 53*40392137SLad Prabhakar #define R9A07G044_CLK_SCI0 18 54*40392137SLad Prabhakar #define R9A07G044_CLK_SCI1 19 55*40392137SLad Prabhakar #define R9A07G044_CLK_GPIO 20 56*40392137SLad Prabhakar #define R9A07G044_CLK_SDHI0 21 57*40392137SLad Prabhakar #define R9A07G044_CLK_SDHI1 22 58*40392137SLad Prabhakar #define R9A07G044_CLK_USB0 23 59*40392137SLad Prabhakar #define R9A07G044_CLK_USB1 24 60*40392137SLad Prabhakar #define R9A07G044_CLK_CANFD 25 61*40392137SLad Prabhakar #define R9A07G044_CLK_SSI0 26 62*40392137SLad Prabhakar #define R9A07G044_CLK_SSI1 27 63*40392137SLad Prabhakar #define R9A07G044_CLK_SSI2 28 64*40392137SLad Prabhakar #define R9A07G044_CLK_SSI3 29 65*40392137SLad Prabhakar #define R9A07G044_CLK_MHU 30 66*40392137SLad Prabhakar #define R9A07G044_CLK_OSTM0 31 67*40392137SLad Prabhakar #define R9A07G044_CLK_OSTM1 32 68*40392137SLad Prabhakar #define R9A07G044_CLK_OSTM2 33 69*40392137SLad Prabhakar #define R9A07G044_CLK_WDT0 34 70*40392137SLad Prabhakar #define R9A07G044_CLK_WDT1 35 71*40392137SLad Prabhakar #define R9A07G044_CLK_WDT2 36 72*40392137SLad Prabhakar #define R9A07G044_CLK_WDT_PON 37 73*40392137SLad Prabhakar #define R9A07G044_CLK_GPU 38 74*40392137SLad Prabhakar #define R9A07G044_CLK_ISU 39 75*40392137SLad Prabhakar #define R9A07G044_CLK_H264 40 76*40392137SLad Prabhakar #define R9A07G044_CLK_CRU 41 77*40392137SLad Prabhakar #define R9A07G044_CLK_MIPI_DSI 42 78*40392137SLad Prabhakar #define R9A07G044_CLK_LCDC 43 79*40392137SLad Prabhakar #define R9A07G044_CLK_SRC 44 80*40392137SLad Prabhakar #define R9A07G044_CLK_RSPI0 45 81*40392137SLad Prabhakar #define R9A07G044_CLK_RSPI1 46 82*40392137SLad Prabhakar #define R9A07G044_CLK_RSPI2 47 83*40392137SLad Prabhakar #define R9A07G044_CLK_ADC 48 84*40392137SLad Prabhakar #define R9A07G044_CLK_TSU_PCLK 49 85*40392137SLad Prabhakar #define R9A07G044_CLK_SPI 50 86*40392137SLad Prabhakar #define R9A07G044_CLK_MIPI_DSI_V 51 87*40392137SLad Prabhakar #define R9A07G044_CLK_MIPI_DSI_PIN 52 88*40392137SLad Prabhakar 89*40392137SLad Prabhakar #endif /* __DT_BINDINGS_CLOCK_R9A07G044_CPG_H__ */ 90