1*f2afa78dSYoshihiro Shimoda /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*f2afa78dSYoshihiro Shimoda /* 3*f2afa78dSYoshihiro Shimoda * Copyright (C) 2022 Renesas Electronics Corp. 4*f2afa78dSYoshihiro Shimoda */ 5*f2afa78dSYoshihiro Shimoda #ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ 6*f2afa78dSYoshihiro Shimoda #define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ 7*f2afa78dSYoshihiro Shimoda 8*f2afa78dSYoshihiro Shimoda #include <dt-bindings/clock/renesas-cpg-mssr.h> 9*f2afa78dSYoshihiro Shimoda 10*f2afa78dSYoshihiro Shimoda /* r8a779g0 CPG Core Clocks */ 11*f2afa78dSYoshihiro Shimoda 12*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZX 0 13*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZS 1 14*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZT 2 15*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZTR 3 16*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2 4 17*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D3 5 18*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D4 6 19*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D1_VIO 7 20*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2_VIO 8 21*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D4_VIO 9 22*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D8_VIO 10 23*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D1_VC 11 24*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2_VC 12 25*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D4_VC 13 26*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2_MM 14 27*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D4_MM 15 28*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2_U3DG 16 29*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D4_U3DG 17 30*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2_RT 18 31*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D3_RT 19 32*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D4_RT 20 33*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D6_RT 21 34*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D24_RT 22 35*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2_PER 23 36*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D3_PER 24 37*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D4_PER 25 38*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D6_PER 26 39*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D12_PER 27 40*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D24_PER 28 41*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D1_HSC 29 42*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2_HSC 30 43*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D4_HSC 31 44*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_S0D2_CC 32 45*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SVD1_IR 33 46*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SVD2_IR 34 47*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SVD1_VIP 35 48*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SVD2_VIP 36 49*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CL 37 50*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CL16M 38 51*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CL16M_MM 39 52*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CL16M_RT 40 53*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CL16M_PER 41 54*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CL16M_HSC 42 55*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_Z0 43 56*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZB3 44 57*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZB3D2 45 58*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZB3D4 46 59*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZG 47 60*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SD0H 48 61*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SD0 49 62*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_RPC 50 63*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_RPCD2 51 64*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_MSO 52 65*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CANFD 53 66*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CSI 54 67*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_FRAY 55 68*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_IPC 56 69*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SASYNCRT 57 70*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SASYNCPERD1 58 71*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SASYNCPERD2 59 72*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_SASYNCPERD4 60 73*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_VIOBUS 61 74*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_VIOBUSD2 62 75*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_VCBUS 63 76*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_VCBUSD2 64 77*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_DSIEXT 65 78*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_DSIREF 66 79*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ADGH 67 80*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_OSC 68 81*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZR0 69 82*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZR1 70 83*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_ZR2 71 84*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_IMPA 72 85*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_IMPAD4 73 86*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CPEX 74 87*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_CBFUSA 75 88*f2afa78dSYoshihiro Shimoda #define R8A779G0_CLK_R 76 89*f2afa78dSYoshihiro Shimoda 90*f2afa78dSYoshihiro Shimoda #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */ 91