19a31fa39STakeshi Kihara /* SPDX-License-Identifier: GPL-2.0 */ 29a31fa39STakeshi Kihara /* 39a31fa39STakeshi Kihara * Copyright (C) 2018 Renesas Electronics Corp. 49a31fa39STakeshi Kihara */ 59a31fa39STakeshi Kihara #ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ 69a31fa39STakeshi Kihara #define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ 79a31fa39STakeshi Kihara 89a31fa39STakeshi Kihara #include <dt-bindings/clock/renesas-cpg-mssr.h> 99a31fa39STakeshi Kihara 109a31fa39STakeshi Kihara /* r8a77990 CPG Core Clocks */ 119a31fa39STakeshi Kihara #define R8A77990_CLK_Z2 0 129a31fa39STakeshi Kihara #define R8A77990_CLK_ZR 1 139a31fa39STakeshi Kihara #define R8A77990_CLK_ZG 2 149a31fa39STakeshi Kihara #define R8A77990_CLK_ZTR 3 159a31fa39STakeshi Kihara #define R8A77990_CLK_ZT 4 169a31fa39STakeshi Kihara #define R8A77990_CLK_ZX 5 179a31fa39STakeshi Kihara #define R8A77990_CLK_S0D1 6 189a31fa39STakeshi Kihara #define R8A77990_CLK_S0D3 7 199a31fa39STakeshi Kihara #define R8A77990_CLK_S0D6 8 209a31fa39STakeshi Kihara #define R8A77990_CLK_S0D12 9 219a31fa39STakeshi Kihara #define R8A77990_CLK_S0D24 10 229a31fa39STakeshi Kihara #define R8A77990_CLK_S1D1 11 239a31fa39STakeshi Kihara #define R8A77990_CLK_S1D2 12 249a31fa39STakeshi Kihara #define R8A77990_CLK_S1D4 13 259a31fa39STakeshi Kihara #define R8A77990_CLK_S2D1 14 269a31fa39STakeshi Kihara #define R8A77990_CLK_S2D2 15 279a31fa39STakeshi Kihara #define R8A77990_CLK_S2D4 16 289a31fa39STakeshi Kihara #define R8A77990_CLK_S3D1 17 299a31fa39STakeshi Kihara #define R8A77990_CLK_S3D2 18 309a31fa39STakeshi Kihara #define R8A77990_CLK_S3D4 19 319a31fa39STakeshi Kihara #define R8A77990_CLK_S0D6C 20 329a31fa39STakeshi Kihara #define R8A77990_CLK_S3D1C 21 339a31fa39STakeshi Kihara #define R8A77990_CLK_S3D2C 22 349a31fa39STakeshi Kihara #define R8A77990_CLK_S3D4C 23 359a31fa39STakeshi Kihara #define R8A77990_CLK_LB 24 369a31fa39STakeshi Kihara #define R8A77990_CLK_CL 25 379a31fa39STakeshi Kihara #define R8A77990_CLK_ZB3 26 389a31fa39STakeshi Kihara #define R8A77990_CLK_ZB3D2 27 399a31fa39STakeshi Kihara #define R8A77990_CLK_CR 28 409a31fa39STakeshi Kihara #define R8A77990_CLK_CRD2 29 419a31fa39STakeshi Kihara #define R8A77990_CLK_SD0H 30 429a31fa39STakeshi Kihara #define R8A77990_CLK_SD0 31 439a31fa39STakeshi Kihara #define R8A77990_CLK_SD1H 32 449a31fa39STakeshi Kihara #define R8A77990_CLK_SD1 33 459a31fa39STakeshi Kihara #define R8A77990_CLK_SD3H 34 469a31fa39STakeshi Kihara #define R8A77990_CLK_SD3 35 479a31fa39STakeshi Kihara #define R8A77990_CLK_RPC 36 489a31fa39STakeshi Kihara #define R8A77990_CLK_RPCD2 37 499a31fa39STakeshi Kihara #define R8A77990_CLK_ZA2 38 509a31fa39STakeshi Kihara #define R8A77990_CLK_ZA8 39 519a31fa39STakeshi Kihara #define R8A77990_CLK_Z2D 40 529a31fa39STakeshi Kihara #define R8A77990_CLK_CANFD 41 539a31fa39STakeshi Kihara #define R8A77990_CLK_MSO 42 549a31fa39STakeshi Kihara #define R8A77990_CLK_R 43 559a31fa39STakeshi Kihara #define R8A77990_CLK_OSC 44 569a31fa39STakeshi Kihara #define R8A77990_CLK_LV0 45 579a31fa39STakeshi Kihara #define R8A77990_CLK_LV1 46 589a31fa39STakeshi Kihara #define R8A77990_CLK_CSI0 47 599a31fa39STakeshi Kihara #define R8A77990_CLK_CP 48 609a31fa39STakeshi Kihara #define R8A77990_CLK_CPEX 49 619a31fa39STakeshi Kihara 629a31fa39STakeshi Kihara #endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */ 63