135b3c462SSergei Shtylyov /* SPDX-License-Identifier: GPL-2.0+ */ 235b3c462SSergei Shtylyov /* 335b3c462SSergei Shtylyov * Copyright (C) 2018 Renesas Electronics Corp. 435b3c462SSergei Shtylyov * Copyright (C) 2018 Cogent Embedded, Inc. 535b3c462SSergei Shtylyov */ 635b3c462SSergei Shtylyov #ifndef __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ 735b3c462SSergei Shtylyov #define __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ 835b3c462SSergei Shtylyov 935b3c462SSergei Shtylyov #include <dt-bindings/clock/renesas-cpg-mssr.h> 1035b3c462SSergei Shtylyov 1135b3c462SSergei Shtylyov /* r8a77980 CPG Core Clocks */ 1235b3c462SSergei Shtylyov #define R8A77980_CLK_Z2 0 1335b3c462SSergei Shtylyov #define R8A77980_CLK_ZR 1 1435b3c462SSergei Shtylyov #define R8A77980_CLK_ZTR 2 1535b3c462SSergei Shtylyov #define R8A77980_CLK_ZTRD2 3 1635b3c462SSergei Shtylyov #define R8A77980_CLK_ZT 4 1735b3c462SSergei Shtylyov #define R8A77980_CLK_ZX 5 1835b3c462SSergei Shtylyov #define R8A77980_CLK_S0D1 6 1935b3c462SSergei Shtylyov #define R8A77980_CLK_S0D2 7 2035b3c462SSergei Shtylyov #define R8A77980_CLK_S0D3 8 2135b3c462SSergei Shtylyov #define R8A77980_CLK_S0D4 9 2235b3c462SSergei Shtylyov #define R8A77980_CLK_S0D6 10 2335b3c462SSergei Shtylyov #define R8A77980_CLK_S0D12 11 2435b3c462SSergei Shtylyov #define R8A77980_CLK_S0D24 12 2535b3c462SSergei Shtylyov #define R8A77980_CLK_S1D1 13 2635b3c462SSergei Shtylyov #define R8A77980_CLK_S1D2 14 2735b3c462SSergei Shtylyov #define R8A77980_CLK_S1D4 15 2835b3c462SSergei Shtylyov #define R8A77980_CLK_S2D1 16 2935b3c462SSergei Shtylyov #define R8A77980_CLK_S2D2 17 3035b3c462SSergei Shtylyov #define R8A77980_CLK_S2D4 18 3135b3c462SSergei Shtylyov #define R8A77980_CLK_S3D1 19 3235b3c462SSergei Shtylyov #define R8A77980_CLK_S3D2 20 3335b3c462SSergei Shtylyov #define R8A77980_CLK_S3D4 21 3435b3c462SSergei Shtylyov #define R8A77980_CLK_LB 22 3535b3c462SSergei Shtylyov #define R8A77980_CLK_CL 23 3635b3c462SSergei Shtylyov #define R8A77980_CLK_ZB3 24 3735b3c462SSergei Shtylyov #define R8A77980_CLK_ZB3D2 25 3835b3c462SSergei Shtylyov #define R8A77980_CLK_ZB3D4 26 3935b3c462SSergei Shtylyov #define R8A77980_CLK_SD0H 27 4035b3c462SSergei Shtylyov #define R8A77980_CLK_SD0 28 4135b3c462SSergei Shtylyov #define R8A77980_CLK_RPC 29 4235b3c462SSergei Shtylyov #define R8A77980_CLK_RPCD2 30 4335b3c462SSergei Shtylyov #define R8A77980_CLK_MSO 31 4435b3c462SSergei Shtylyov #define R8A77980_CLK_CANFD 32 4535b3c462SSergei Shtylyov #define R8A77980_CLK_CSI0 33 4635b3c462SSergei Shtylyov #define R8A77980_CLK_CP 34 4735b3c462SSergei Shtylyov #define R8A77980_CLK_CPEX 35 4835b3c462SSergei Shtylyov #define R8A77980_CLK_R 36 4935b3c462SSergei Shtylyov #define R8A77980_CLK_OSC 37 5035b3c462SSergei Shtylyov 5135b3c462SSergei Shtylyov #endif /* __DT_BINDINGS_CLOCK_R8A77980_CPG_MSSR_H__ */ 52