10b05ad22SGeert Uytterhoeven /* SPDX-License-Identifier: GPL-2.0+ 20b05ad22SGeert Uytterhoeven * 30b05ad22SGeert Uytterhoeven * Copyright (C) 2019 Renesas Electronics Corp. 40b05ad22SGeert Uytterhoeven */ 50b05ad22SGeert Uytterhoeven #ifndef __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ 60b05ad22SGeert Uytterhoeven #define __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ 70b05ad22SGeert Uytterhoeven 80b05ad22SGeert Uytterhoeven #include <dt-bindings/clock/renesas-cpg-mssr.h> 90b05ad22SGeert Uytterhoeven 100b05ad22SGeert Uytterhoeven /* r8a77961 CPG Core Clocks */ 110b05ad22SGeert Uytterhoeven #define R8A77961_CLK_Z 0 120b05ad22SGeert Uytterhoeven #define R8A77961_CLK_Z2 1 130b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZR 2 140b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZG 3 150b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZTR 4 160b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZTRD2 5 170b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZT 6 180b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZX 7 190b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D1 8 200b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D2 9 210b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D3 10 220b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D4 11 230b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D6 12 240b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D8 13 250b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S0D12 14 260b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S1D1 15 270b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S1D2 16 280b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S1D4 17 290b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S2D1 18 300b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S2D2 19 310b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S2D4 20 320b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S3D1 21 330b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S3D2 22 340b05ad22SGeert Uytterhoeven #define R8A77961_CLK_S3D4 23 350b05ad22SGeert Uytterhoeven #define R8A77961_CLK_LB 24 360b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CL 25 370b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZB3 26 380b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZB3D2 27 390b05ad22SGeert Uytterhoeven #define R8A77961_CLK_ZB3D4 28 400b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CR 29 410b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CRD2 30 420b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD0H 31 430b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD0 32 440b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD1H 33 450b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD1 34 460b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD2H 35 470b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD2 36 480b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD3H 37 490b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SD3 38 500b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SSP2 39 510b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SSP1 40 520b05ad22SGeert Uytterhoeven #define R8A77961_CLK_SSPRS 41 530b05ad22SGeert Uytterhoeven #define R8A77961_CLK_RPC 42 540b05ad22SGeert Uytterhoeven #define R8A77961_CLK_RPCD2 43 550b05ad22SGeert Uytterhoeven #define R8A77961_CLK_MSO 44 560b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CANFD 45 570b05ad22SGeert Uytterhoeven #define R8A77961_CLK_HDMI 46 580b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CSI0 47 590b05ad22SGeert Uytterhoeven /* CLK_CSIREF was removed */ 600b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CP 49 610b05ad22SGeert Uytterhoeven #define R8A77961_CLK_CPEX 50 620b05ad22SGeert Uytterhoeven #define R8A77961_CLK_R 51 630b05ad22SGeert Uytterhoeven #define R8A77961_CLK_OSC 52 640b05ad22SGeert Uytterhoeven 650b05ad22SGeert Uytterhoeven #endif /* __DT_BINDINGS_CLOCK_R8A77961_CPG_MSSR_H__ */ 66