15d169ce7SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0+ 2972610fbSGeert Uytterhoeven * 35d169ce7SKuninori Morimoto * Copyright (C) 2016 Renesas Electronics Corp. 4972610fbSGeert Uytterhoeven */ 5972610fbSGeert Uytterhoeven #ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ 6972610fbSGeert Uytterhoeven #define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ 7972610fbSGeert Uytterhoeven 8972610fbSGeert Uytterhoeven #include <dt-bindings/clock/renesas-cpg-mssr.h> 9972610fbSGeert Uytterhoeven 10972610fbSGeert Uytterhoeven /* r8a7796 CPG Core Clocks */ 11972610fbSGeert Uytterhoeven #define R8A7796_CLK_Z 0 12972610fbSGeert Uytterhoeven #define R8A7796_CLK_Z2 1 13972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZR 2 14972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZG 3 15972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZTR 4 16972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZTRD2 5 17972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZT 6 18972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZX 7 19972610fbSGeert Uytterhoeven #define R8A7796_CLK_S0D1 8 20972610fbSGeert Uytterhoeven #define R8A7796_CLK_S0D2 9 21972610fbSGeert Uytterhoeven #define R8A7796_CLK_S0D3 10 22972610fbSGeert Uytterhoeven #define R8A7796_CLK_S0D4 11 23972610fbSGeert Uytterhoeven #define R8A7796_CLK_S0D6 12 24972610fbSGeert Uytterhoeven #define R8A7796_CLK_S0D8 13 25972610fbSGeert Uytterhoeven #define R8A7796_CLK_S0D12 14 26972610fbSGeert Uytterhoeven #define R8A7796_CLK_S1D1 15 27972610fbSGeert Uytterhoeven #define R8A7796_CLK_S1D2 16 28972610fbSGeert Uytterhoeven #define R8A7796_CLK_S1D4 17 29972610fbSGeert Uytterhoeven #define R8A7796_CLK_S2D1 18 30972610fbSGeert Uytterhoeven #define R8A7796_CLK_S2D2 19 31972610fbSGeert Uytterhoeven #define R8A7796_CLK_S2D4 20 32972610fbSGeert Uytterhoeven #define R8A7796_CLK_S3D1 21 33972610fbSGeert Uytterhoeven #define R8A7796_CLK_S3D2 22 34972610fbSGeert Uytterhoeven #define R8A7796_CLK_S3D4 23 35972610fbSGeert Uytterhoeven #define R8A7796_CLK_LB 24 36972610fbSGeert Uytterhoeven #define R8A7796_CLK_CL 25 37972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZB3 26 38972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZB3D2 27 39972610fbSGeert Uytterhoeven #define R8A7796_CLK_ZB3D4 28 40972610fbSGeert Uytterhoeven #define R8A7796_CLK_CR 29 41972610fbSGeert Uytterhoeven #define R8A7796_CLK_CRD2 30 42972610fbSGeert Uytterhoeven #define R8A7796_CLK_SD0H 31 43972610fbSGeert Uytterhoeven #define R8A7796_CLK_SD0 32 44972610fbSGeert Uytterhoeven #define R8A7796_CLK_SD1H 33 45972610fbSGeert Uytterhoeven #define R8A7796_CLK_SD1 34 46972610fbSGeert Uytterhoeven #define R8A7796_CLK_SD2H 35 47972610fbSGeert Uytterhoeven #define R8A7796_CLK_SD2 36 48972610fbSGeert Uytterhoeven #define R8A7796_CLK_SD3H 37 49972610fbSGeert Uytterhoeven #define R8A7796_CLK_SD3 38 50972610fbSGeert Uytterhoeven #define R8A7796_CLK_SSP2 39 51972610fbSGeert Uytterhoeven #define R8A7796_CLK_SSP1 40 52972610fbSGeert Uytterhoeven #define R8A7796_CLK_SSPRS 41 53972610fbSGeert Uytterhoeven #define R8A7796_CLK_RPC 42 54972610fbSGeert Uytterhoeven #define R8A7796_CLK_RPCD2 43 55972610fbSGeert Uytterhoeven #define R8A7796_CLK_MSO 44 56972610fbSGeert Uytterhoeven #define R8A7796_CLK_CANFD 45 57972610fbSGeert Uytterhoeven #define R8A7796_CLK_HDMI 46 58972610fbSGeert Uytterhoeven #define R8A7796_CLK_CSI0 47 59972610fbSGeert Uytterhoeven #define R8A7796_CLK_CSIREF 48 60972610fbSGeert Uytterhoeven #define R8A7796_CLK_CP 49 61972610fbSGeert Uytterhoeven #define R8A7796_CLK_CPEX 50 62972610fbSGeert Uytterhoeven #define R8A7796_CLK_R 51 63972610fbSGeert Uytterhoeven #define R8A7796_CLK_OSC 52 64972610fbSGeert Uytterhoeven 65972610fbSGeert Uytterhoeven #endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ 66