10ea86f5aSGeert Uytterhoeven /* 20ea86f5aSGeert Uytterhoeven * Copyright (C) 2015 Renesas Electronics Corp. 30ea86f5aSGeert Uytterhoeven * 40ea86f5aSGeert Uytterhoeven * This program is free software; you can redistribute it and/or modify 50ea86f5aSGeert Uytterhoeven * it under the terms of the GNU General Public License as published by 60ea86f5aSGeert Uytterhoeven * the Free Software Foundation; either version 2 of the License, or 70ea86f5aSGeert Uytterhoeven * (at your option) any later version. 80ea86f5aSGeert Uytterhoeven */ 90ea86f5aSGeert Uytterhoeven 100ea86f5aSGeert Uytterhoeven #ifndef __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 110ea86f5aSGeert Uytterhoeven #define __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ 120ea86f5aSGeert Uytterhoeven 130ea86f5aSGeert Uytterhoeven #include <dt-bindings/clock/renesas-cpg-mssr.h> 140ea86f5aSGeert Uytterhoeven 150ea86f5aSGeert Uytterhoeven /* r8a7794 CPG Core Clocks */ 160ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_Z2 0 170ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZG 1 180ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZTR 2 190ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZTRD2 3 200ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZT 4 210ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZX 5 220ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZS 6 230ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_HP 7 240ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_I 8 250ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_B 9 260ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_LB 10 270ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_P 11 280ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_CL 12 290ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_CP 13 300ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_M2 14 310ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ADSP 15 320ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZB3 16 330ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_ZB3D2 17 340ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_DDR 18 350ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_SDH 19 360ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_SD0 20 370ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_SD2 21 380ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_SD3 22 390ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_MMC0 23 400ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_MP 24 410ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_QSPI 25 420ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_CPEX 26 430ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_RCAN 27 440ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_R 28 450ea86f5aSGeert Uytterhoeven #define R8A7794_CLK_OSC 29 460ea86f5aSGeert Uytterhoeven 470ea86f5aSGeert Uytterhoeven #endif /* __DT_BINDINGS_CLOCK_R8A7794_CPG_MSSR_H__ */ 48