1 /*
2  * Copyright (C) 2014 Renesas Electronics Corporation
3  * Copyright 2013 Ideas On Board SPRL
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation; either version 2 of the License, or
8  * (at your option) any later version.
9  */
10 
11 #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
12 #define __DT_BINDINGS_CLOCK_R8A7794_H__
13 
14 /* CPG */
15 #define R8A7794_CLK_MAIN		0
16 #define R8A7794_CLK_PLL0		1
17 #define R8A7794_CLK_PLL1		2
18 #define R8A7794_CLK_PLL3		3
19 #define R8A7794_CLK_LB			4
20 #define R8A7794_CLK_QSPI		5
21 #define R8A7794_CLK_SDH			6
22 #define R8A7794_CLK_SD0			7
23 #define R8A7794_CLK_Z			8
24 
25 /* MSTP0 */
26 #define R8A7794_CLK_MSIOF0		0
27 
28 /* MSTP1 */
29 #define R8A7794_CLK_VCP0		1
30 #define R8A7794_CLK_VPC0		3
31 #define R8A7794_CLK_TMU1		11
32 #define R8A7794_CLK_3DG			12
33 #define R8A7794_CLK_2DDMAC		15
34 #define R8A7794_CLK_FDP1_0		19
35 #define R8A7794_CLK_TMU3		21
36 #define R8A7794_CLK_TMU2		22
37 #define R8A7794_CLK_CMT0		24
38 #define R8A7794_CLK_TMU0		25
39 #define R8A7794_CLK_VSP1_DU0		28
40 #define R8A7794_CLK_VSP1_S		31
41 
42 /* MSTP2 */
43 #define R8A7794_CLK_SCIFA2		2
44 #define R8A7794_CLK_SCIFA1		3
45 #define R8A7794_CLK_SCIFA0		4
46 #define R8A7794_CLK_MSIOF2		5
47 #define R8A7794_CLK_SCIFB0		6
48 #define R8A7794_CLK_SCIFB1		7
49 #define R8A7794_CLK_MSIOF1		8
50 #define R8A7794_CLK_SCIFB2		16
51 #define R8A7794_CLK_SYS_DMAC1		18
52 #define R8A7794_CLK_SYS_DMAC0		19
53 
54 /* MSTP3 */
55 #define R8A7794_CLK_SDHI2		11
56 #define R8A7794_CLK_SDHI1		12
57 #define R8A7794_CLK_SDHI0		14
58 #define R8A7794_CLK_MMCIF0		15
59 #define R8A7794_CLK_CMT1		29
60 #define R8A7794_CLK_USBDMAC0		30
61 #define R8A7794_CLK_USBDMAC1		31
62 
63 /* MSTP5 */
64 #define R8A7794_CLK_THERMAL		22
65 #define R8A7794_CLK_PWM			23
66 
67 /* MSTP7 */
68 #define R8A7794_CLK_EHCI		3
69 #define R8A7794_CLK_HSUSB		4
70 #define R8A7794_CLK_HSCIF2		13
71 #define R8A7794_CLK_SCIF5		14
72 #define R8A7794_CLK_SCIF4		15
73 #define R8A7794_CLK_HSCIF1		16
74 #define R8A7794_CLK_HSCIF0		17
75 #define R8A7794_CLK_SCIF3		18
76 #define R8A7794_CLK_SCIF2		19
77 #define R8A7794_CLK_SCIF1		20
78 #define R8A7794_CLK_SCIF0		21
79 
80 /* MSTP8 */
81 #define R8A7794_CLK_VIN1		10
82 #define R8A7794_CLK_VIN0		11
83 #define R8A7794_CLK_ETHER		13
84 
85 /* MSTP9 */
86 #define R8A7794_CLK_GPIO6		5
87 #define R8A7794_CLK_GPIO5		7
88 #define R8A7794_CLK_GPIO4		8
89 #define R8A7794_CLK_GPIO3		9
90 #define R8A7794_CLK_GPIO2		10
91 #define R8A7794_CLK_GPIO1		11
92 #define R8A7794_CLK_GPIO0		12
93 #define R8A7794_CLK_QSPI_MOD		17
94 #define R8A7794_CLK_I2C5		25
95 #define R8A7794_CLK_I2C4		27
96 #define R8A7794_CLK_I2C3		28
97 #define R8A7794_CLK_I2C2		29
98 #define R8A7794_CLK_I2C1		30
99 #define R8A7794_CLK_I2C0		31
100 
101 /* MSTP11 */
102 #define R8A7794_CLK_SCIFA3		6
103 #define R8A7794_CLK_SCIFA4		7
104 #define R8A7794_CLK_SCIFA5		8
105 
106 #endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */
107