15d169ce7SKuninori Morimoto /* SPDX-License-Identifier: GPL-2.0+ 25d169ce7SKuninori Morimoto * 30dce5454SUlrich Hecht * Copyright (C) 2014 Renesas Electronics Corporation 40dce5454SUlrich Hecht * Copyright 2013 Ideas On Board SPRL 50dce5454SUlrich Hecht */ 60dce5454SUlrich Hecht 70dce5454SUlrich Hecht #ifndef __DT_BINDINGS_CLOCK_R8A7794_H__ 80dce5454SUlrich Hecht #define __DT_BINDINGS_CLOCK_R8A7794_H__ 90dce5454SUlrich Hecht 100dce5454SUlrich Hecht /* CPG */ 110dce5454SUlrich Hecht #define R8A7794_CLK_MAIN 0 120dce5454SUlrich Hecht #define R8A7794_CLK_PLL0 1 130dce5454SUlrich Hecht #define R8A7794_CLK_PLL1 2 140dce5454SUlrich Hecht #define R8A7794_CLK_PLL3 3 150dce5454SUlrich Hecht #define R8A7794_CLK_LB 4 160dce5454SUlrich Hecht #define R8A7794_CLK_QSPI 5 170dce5454SUlrich Hecht #define R8A7794_CLK_SDH 6 180dce5454SUlrich Hecht #define R8A7794_CLK_SD0 7 1968cc085aSSergei Shtylyov #define R8A7794_CLK_RCAN 8 200dce5454SUlrich Hecht 210dce5454SUlrich Hecht /* MSTP0 */ 220dce5454SUlrich Hecht #define R8A7794_CLK_MSIOF0 0 230dce5454SUlrich Hecht 240dce5454SUlrich Hecht /* MSTP1 */ 25dc3cf93dSYoshifumi Hosoya #define R8A7794_CLK_VCP0 1 26dc3cf93dSYoshifumi Hosoya #define R8A7794_CLK_VPC0 3 270dce5454SUlrich Hecht #define R8A7794_CLK_TMU1 11 283e58a542SKouei Abe #define R8A7794_CLK_3DG 12 29dc3cf93dSYoshifumi Hosoya #define R8A7794_CLK_2DDMAC 15 30dc3cf93dSYoshifumi Hosoya #define R8A7794_CLK_FDP1_0 19 310dce5454SUlrich Hecht #define R8A7794_CLK_TMU3 21 320dce5454SUlrich Hecht #define R8A7794_CLK_TMU2 22 330dce5454SUlrich Hecht #define R8A7794_CLK_CMT0 24 340dce5454SUlrich Hecht #define R8A7794_CLK_TMU0 25 35dc3cf93dSYoshifumi Hosoya #define R8A7794_CLK_VSP1_DU0 28 36dc3cf93dSYoshifumi Hosoya #define R8A7794_CLK_VSP1_S 31 370dce5454SUlrich Hecht 380dce5454SUlrich Hecht /* MSTP2 */ 390dce5454SUlrich Hecht #define R8A7794_CLK_SCIFA2 2 400dce5454SUlrich Hecht #define R8A7794_CLK_SCIFA1 3 410dce5454SUlrich Hecht #define R8A7794_CLK_SCIFA0 4 420dce5454SUlrich Hecht #define R8A7794_CLK_MSIOF2 5 430dce5454SUlrich Hecht #define R8A7794_CLK_SCIFB0 6 440dce5454SUlrich Hecht #define R8A7794_CLK_SCIFB1 7 450dce5454SUlrich Hecht #define R8A7794_CLK_MSIOF1 8 460dce5454SUlrich Hecht #define R8A7794_CLK_SCIFB2 16 47be16cd38SHiroyuki Yokoyama #define R8A7794_CLK_SYS_DMAC1 18 48be16cd38SHiroyuki Yokoyama #define R8A7794_CLK_SYS_DMAC0 19 490dce5454SUlrich Hecht 500dce5454SUlrich Hecht /* MSTP3 */ 518e181633SShinobu Uehara #define R8A7794_CLK_SDHI2 11 528e181633SShinobu Uehara #define R8A7794_CLK_SDHI1 12 538e181633SShinobu Uehara #define R8A7794_CLK_SDHI0 14 54deac150cSShinobu Uehara #define R8A7794_CLK_MMCIF0 15 55a856b195SSimon Horman #define R8A7794_CLK_IIC0 18 56a856b195SSimon Horman #define R8A7794_CLK_IIC1 23 570dce5454SUlrich Hecht #define R8A7794_CLK_CMT1 29 5822a9b44fSKazuya Mizuguchi #define R8A7794_CLK_USBDMAC0 30 5922a9b44fSKazuya Mizuguchi #define R8A7794_CLK_USBDMAC1 31 600dce5454SUlrich Hecht 611c5ca5dbSGeert Uytterhoeven /* MSTP4 */ 621c5ca5dbSGeert Uytterhoeven #define R8A7794_CLK_IRQC 7 63133a3f1aSGeert Uytterhoeven #define R8A7794_CLK_INTC_SYS 8 641c5ca5dbSGeert Uytterhoeven 650dce5454SUlrich Hecht /* MSTP5 */ 662a29f9d6SSergei Shtylyov #define R8A7794_CLK_AUDIO_DMAC0 2 670dce5454SUlrich Hecht #define R8A7794_CLK_PWM 23 680dce5454SUlrich Hecht 690dce5454SUlrich Hecht /* MSTP7 */ 70c7bab9f9SShinobu Uehara #define R8A7794_CLK_EHCI 3 71c7bab9f9SShinobu Uehara #define R8A7794_CLK_HSUSB 4 720dce5454SUlrich Hecht #define R8A7794_CLK_HSCIF2 13 730dce5454SUlrich Hecht #define R8A7794_CLK_SCIF5 14 740dce5454SUlrich Hecht #define R8A7794_CLK_SCIF4 15 750dce5454SUlrich Hecht #define R8A7794_CLK_HSCIF1 16 760dce5454SUlrich Hecht #define R8A7794_CLK_HSCIF0 17 770dce5454SUlrich Hecht #define R8A7794_CLK_SCIF3 18 780dce5454SUlrich Hecht #define R8A7794_CLK_SCIF2 19 790dce5454SUlrich Hecht #define R8A7794_CLK_SCIF1 20 800dce5454SUlrich Hecht #define R8A7794_CLK_SCIF0 21 811764f808SGeert Uytterhoeven #define R8A7794_CLK_DU1 23 829859cd3bSLaurent Pinchart #define R8A7794_CLK_DU0 24 830dce5454SUlrich Hecht 840dce5454SUlrich Hecht /* MSTP8 */ 85148ebf47SKoji Matsuoka #define R8A7794_CLK_VIN1 10 86148ebf47SKoji Matsuoka #define R8A7794_CLK_VIN0 11 87255a4042SSergei Shtylyov #define R8A7794_CLK_ETHERAVB 12 880dce5454SUlrich Hecht #define R8A7794_CLK_ETHER 13 890dce5454SUlrich Hecht 900dce5454SUlrich Hecht /* MSTP9 */ 910dce5454SUlrich Hecht #define R8A7794_CLK_GPIO6 5 920dce5454SUlrich Hecht #define R8A7794_CLK_GPIO5 7 930dce5454SUlrich Hecht #define R8A7794_CLK_GPIO4 8 940dce5454SUlrich Hecht #define R8A7794_CLK_GPIO3 9 950dce5454SUlrich Hecht #define R8A7794_CLK_GPIO2 10 960dce5454SUlrich Hecht #define R8A7794_CLK_GPIO1 11 970dce5454SUlrich Hecht #define R8A7794_CLK_GPIO0 12 98e980f941SSimon Horman #define R8A7794_CLK_RCAN1 15 99e980f941SSimon Horman #define R8A7794_CLK_RCAN0 16 1003281480bSHisashi Nakamura #define R8A7794_CLK_QSPI_MOD 17 101c5d82c99SKoji Matsuoka #define R8A7794_CLK_I2C5 25 102c5d82c99SKoji Matsuoka #define R8A7794_CLK_I2C4 27 103c5d82c99SKoji Matsuoka #define R8A7794_CLK_I2C3 28 104c5d82c99SKoji Matsuoka #define R8A7794_CLK_I2C2 29 105c5d82c99SKoji Matsuoka #define R8A7794_CLK_I2C1 30 106c5d82c99SKoji Matsuoka #define R8A7794_CLK_I2C0 31 1070dce5454SUlrich Hecht 108975fb77fSSergei Shtylyov /* MSTP10 */ 109975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI_ALL 5 110975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI9 6 111975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI8 7 112975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI7 8 113975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI6 9 114975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI5 10 115975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI4 11 116975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI3 12 117975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI2 13 118975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI1 14 119975fb77fSSergei Shtylyov #define R8A7794_CLK_SSI0 15 120975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_ALL 17 121975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_DVC1 18 122975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_DVC0 19 123975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_CTU1_MIX1 20 124975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_CTU0_MIX0 21 125975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_SRC6 25 126975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_SRC5 26 127975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_SRC4 27 128975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_SRC3 28 129975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_SRC2 29 130975fb77fSSergei Shtylyov #define R8A7794_CLK_SCU_SRC1 30 131975fb77fSSergei Shtylyov 1320dce5454SUlrich Hecht /* MSTP11 */ 1330dce5454SUlrich Hecht #define R8A7794_CLK_SCIFA3 6 1340dce5454SUlrich Hecht #define R8A7794_CLK_SCIFA4 7 1350dce5454SUlrich Hecht #define R8A7794_CLK_SCIFA5 8 1360dce5454SUlrich Hecht 1370dce5454SUlrich Hecht #endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */ 138