12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2de0fae60SSergei Shtylyov /* 3de0fae60SSergei Shtylyov * Copyright (C) 2016 Cogent Embedded, Inc. 4de0fae60SSergei Shtylyov */ 5de0fae60SSergei Shtylyov 6de0fae60SSergei Shtylyov #ifndef __DT_BINDINGS_CLOCK_R8A7792_H__ 7de0fae60SSergei Shtylyov #define __DT_BINDINGS_CLOCK_R8A7792_H__ 8de0fae60SSergei Shtylyov 9de0fae60SSergei Shtylyov /* CPG */ 10de0fae60SSergei Shtylyov #define R8A7792_CLK_MAIN 0 11de0fae60SSergei Shtylyov #define R8A7792_CLK_PLL0 1 12de0fae60SSergei Shtylyov #define R8A7792_CLK_PLL1 2 13de0fae60SSergei Shtylyov #define R8A7792_CLK_PLL3 3 14de0fae60SSergei Shtylyov #define R8A7792_CLK_LB 4 15de0fae60SSergei Shtylyov #define R8A7792_CLK_QSPI 5 16de0fae60SSergei Shtylyov 17de0fae60SSergei Shtylyov /* MSTP0 */ 18de0fae60SSergei Shtylyov #define R8A7792_CLK_MSIOF0 0 19de0fae60SSergei Shtylyov 20de0fae60SSergei Shtylyov /* MSTP1 */ 21eebc8e2cSSergei Shtylyov #define R8A7792_CLK_JPU 6 22de0fae60SSergei Shtylyov #define R8A7792_CLK_TMU1 11 23de0fae60SSergei Shtylyov #define R8A7792_CLK_TMU3 21 24de0fae60SSergei Shtylyov #define R8A7792_CLK_TMU2 22 25de0fae60SSergei Shtylyov #define R8A7792_CLK_CMT0 24 26de0fae60SSergei Shtylyov #define R8A7792_CLK_TMU0 25 27de0fae60SSergei Shtylyov #define R8A7792_CLK_VSP1DU1 27 28de0fae60SSergei Shtylyov #define R8A7792_CLK_VSP1DU0 28 29de0fae60SSergei Shtylyov #define R8A7792_CLK_VSP1_SY 31 30de0fae60SSergei Shtylyov 31de0fae60SSergei Shtylyov /* MSTP2 */ 32de0fae60SSergei Shtylyov #define R8A7792_CLK_MSIOF1 8 33de0fae60SSergei Shtylyov #define R8A7792_CLK_SYS_DMAC1 18 34de0fae60SSergei Shtylyov #define R8A7792_CLK_SYS_DMAC0 19 35de0fae60SSergei Shtylyov 36de0fae60SSergei Shtylyov /* MSTP3 */ 37de0fae60SSergei Shtylyov #define R8A7792_CLK_TPU0 4 38de0fae60SSergei Shtylyov #define R8A7792_CLK_SDHI0 14 39de0fae60SSergei Shtylyov #define R8A7792_CLK_CMT1 29 40de0fae60SSergei Shtylyov 41de0fae60SSergei Shtylyov /* MSTP4 */ 42de0fae60SSergei Shtylyov #define R8A7792_CLK_IRQC 7 4390dce542SGeert Uytterhoeven #define R8A7792_CLK_INTC_SYS 8 44de0fae60SSergei Shtylyov 45de0fae60SSergei Shtylyov /* MSTP5 */ 46de0fae60SSergei Shtylyov #define R8A7792_CLK_AUDIO_DMAC0 2 47de0fae60SSergei Shtylyov #define R8A7792_CLK_THERMAL 22 48de0fae60SSergei Shtylyov #define R8A7792_CLK_PWM 23 49de0fae60SSergei Shtylyov 50de0fae60SSergei Shtylyov /* MSTP7 */ 51de0fae60SSergei Shtylyov #define R8A7792_CLK_HSCIF1 16 52de0fae60SSergei Shtylyov #define R8A7792_CLK_HSCIF0 17 53de0fae60SSergei Shtylyov #define R8A7792_CLK_SCIF3 18 54de0fae60SSergei Shtylyov #define R8A7792_CLK_SCIF2 19 55de0fae60SSergei Shtylyov #define R8A7792_CLK_SCIF1 20 56de0fae60SSergei Shtylyov #define R8A7792_CLK_SCIF0 21 57de0fae60SSergei Shtylyov #define R8A7792_CLK_DU1 23 58de0fae60SSergei Shtylyov #define R8A7792_CLK_DU0 24 59de0fae60SSergei Shtylyov 60de0fae60SSergei Shtylyov /* MSTP8 */ 61de0fae60SSergei Shtylyov #define R8A7792_CLK_VIN5 4 62de0fae60SSergei Shtylyov #define R8A7792_CLK_VIN4 5 63de0fae60SSergei Shtylyov #define R8A7792_CLK_VIN3 8 64de0fae60SSergei Shtylyov #define R8A7792_CLK_VIN2 9 65de0fae60SSergei Shtylyov #define R8A7792_CLK_VIN1 10 66de0fae60SSergei Shtylyov #define R8A7792_CLK_VIN0 11 67de0fae60SSergei Shtylyov #define R8A7792_CLK_ETHERAVB 12 68de0fae60SSergei Shtylyov 69de0fae60SSergei Shtylyov /* MSTP9 */ 70de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO7 4 71de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO6 5 72de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO5 7 73de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO4 8 74de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO3 9 75de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO2 10 76de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO1 11 77de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO0 12 78de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO11 13 79de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO10 14 80de0fae60SSergei Shtylyov #define R8A7792_CLK_CAN1 15 81de0fae60SSergei Shtylyov #define R8A7792_CLK_CAN0 16 82de0fae60SSergei Shtylyov #define R8A7792_CLK_QSPI_MOD 17 83de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO9 19 84de0fae60SSergei Shtylyov #define R8A7792_CLK_GPIO8 21 85de0fae60SSergei Shtylyov #define R8A7792_CLK_I2C5 25 86de0fae60SSergei Shtylyov #define R8A7792_CLK_IICDVFS 26 87de0fae60SSergei Shtylyov #define R8A7792_CLK_I2C4 27 88de0fae60SSergei Shtylyov #define R8A7792_CLK_I2C3 28 89de0fae60SSergei Shtylyov #define R8A7792_CLK_I2C2 29 90de0fae60SSergei Shtylyov #define R8A7792_CLK_I2C1 30 91de0fae60SSergei Shtylyov #define R8A7792_CLK_I2C0 31 92de0fae60SSergei Shtylyov 93de0fae60SSergei Shtylyov /* MSTP10 */ 94de0fae60SSergei Shtylyov #define R8A7792_CLK_SSI_ALL 5 95de0fae60SSergei Shtylyov #define R8A7792_CLK_SSI4 11 96de0fae60SSergei Shtylyov #define R8A7792_CLK_SSI3 12 97de0fae60SSergei Shtylyov 98de0fae60SSergei Shtylyov #endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */ 99