1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright 2013 Ideas On Board SPRL 4 */ 5 6 #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ 7 #define __DT_BINDINGS_CLOCK_R8A7790_H__ 8 9 /* CPG */ 10 #define R8A7790_CLK_MAIN 0 11 #define R8A7790_CLK_PLL0 1 12 #define R8A7790_CLK_PLL1 2 13 #define R8A7790_CLK_PLL3 3 14 #define R8A7790_CLK_LB 4 15 #define R8A7790_CLK_QSPI 5 16 #define R8A7790_CLK_SDH 6 17 #define R8A7790_CLK_SD0 7 18 #define R8A7790_CLK_SD1 8 19 #define R8A7790_CLK_Z 9 20 #define R8A7790_CLK_RCAN 10 21 #define R8A7790_CLK_ADSP 11 22 23 /* MSTP0 */ 24 #define R8A7790_CLK_MSIOF0 0 25 26 /* MSTP1 */ 27 #define R8A7790_CLK_VCP1 0 28 #define R8A7790_CLK_VCP0 1 29 #define R8A7790_CLK_VPC1 2 30 #define R8A7790_CLK_VPC0 3 31 #define R8A7790_CLK_JPU 6 32 #define R8A7790_CLK_SSP1 9 33 #define R8A7790_CLK_TMU1 11 34 #define R8A7790_CLK_3DG 12 35 #define R8A7790_CLK_2DDMAC 15 36 #define R8A7790_CLK_FDP1_2 17 37 #define R8A7790_CLK_FDP1_1 18 38 #define R8A7790_CLK_FDP1_0 19 39 #define R8A7790_CLK_TMU3 21 40 #define R8A7790_CLK_TMU2 22 41 #define R8A7790_CLK_CMT0 24 42 #define R8A7790_CLK_TMU0 25 43 #define R8A7790_CLK_VSP1_DU1 27 44 #define R8A7790_CLK_VSP1_DU0 28 45 #define R8A7790_CLK_VSP1_R 30 46 #define R8A7790_CLK_VSP1_S 31 47 48 /* MSTP2 */ 49 #define R8A7790_CLK_SCIFA2 2 50 #define R8A7790_CLK_SCIFA1 3 51 #define R8A7790_CLK_SCIFA0 4 52 #define R8A7790_CLK_MSIOF2 5 53 #define R8A7790_CLK_SCIFB0 6 54 #define R8A7790_CLK_SCIFB1 7 55 #define R8A7790_CLK_MSIOF1 8 56 #define R8A7790_CLK_MSIOF3 15 57 #define R8A7790_CLK_SCIFB2 16 58 #define R8A7790_CLK_SYS_DMAC1 18 59 #define R8A7790_CLK_SYS_DMAC0 19 60 61 /* MSTP3 */ 62 #define R8A7790_CLK_IIC2 0 63 #define R8A7790_CLK_TPU0 4 64 #define R8A7790_CLK_MMCIF1 5 65 #define R8A7790_CLK_SCIF2 10 66 #define R8A7790_CLK_SDHI3 11 67 #define R8A7790_CLK_SDHI2 12 68 #define R8A7790_CLK_SDHI1 13 69 #define R8A7790_CLK_SDHI0 14 70 #define R8A7790_CLK_MMCIF0 15 71 #define R8A7790_CLK_IIC0 18 72 #define R8A7790_CLK_PCIEC 19 73 #define R8A7790_CLK_IIC1 23 74 #define R8A7790_CLK_SSUSB 28 75 #define R8A7790_CLK_CMT1 29 76 #define R8A7790_CLK_USBDMAC0 30 77 #define R8A7790_CLK_USBDMAC1 31 78 79 /* MSTP4 */ 80 #define R8A7790_CLK_IRQC 7 81 #define R8A7790_CLK_INTC_SYS 8 82 83 /* MSTP5 */ 84 #define R8A7790_CLK_AUDIO_DMAC1 1 85 #define R8A7790_CLK_AUDIO_DMAC0 2 86 #define R8A7790_CLK_ADSP_MOD 6 87 #define R8A7790_CLK_THERMAL 22 88 #define R8A7790_CLK_PWM 23 89 90 /* MSTP7 */ 91 #define R8A7790_CLK_EHCI 3 92 #define R8A7790_CLK_HSUSB 4 93 #define R8A7790_CLK_HSCIF1 16 94 #define R8A7790_CLK_HSCIF0 17 95 #define R8A7790_CLK_SCIF1 20 96 #define R8A7790_CLK_SCIF0 21 97 #define R8A7790_CLK_DU2 22 98 #define R8A7790_CLK_DU1 23 99 #define R8A7790_CLK_DU0 24 100 #define R8A7790_CLK_LVDS1 25 101 #define R8A7790_CLK_LVDS0 26 102 103 /* MSTP8 */ 104 #define R8A7790_CLK_MLB 2 105 #define R8A7790_CLK_VIN3 8 106 #define R8A7790_CLK_VIN2 9 107 #define R8A7790_CLK_VIN1 10 108 #define R8A7790_CLK_VIN0 11 109 #define R8A7790_CLK_ETHERAVB 12 110 #define R8A7790_CLK_ETHER 13 111 #define R8A7790_CLK_SATA1 14 112 #define R8A7790_CLK_SATA0 15 113 114 /* MSTP9 */ 115 #define R8A7790_CLK_GPIO5 7 116 #define R8A7790_CLK_GPIO4 8 117 #define R8A7790_CLK_GPIO3 9 118 #define R8A7790_CLK_GPIO2 10 119 #define R8A7790_CLK_GPIO1 11 120 #define R8A7790_CLK_GPIO0 12 121 #define R8A7790_CLK_RCAN1 15 122 #define R8A7790_CLK_RCAN0 16 123 #define R8A7790_CLK_QSPI_MOD 17 124 #define R8A7790_CLK_IICDVFS 26 125 #define R8A7790_CLK_I2C3 28 126 #define R8A7790_CLK_I2C2 29 127 #define R8A7790_CLK_I2C1 30 128 #define R8A7790_CLK_I2C0 31 129 130 /* MSTP10 */ 131 #define R8A7790_CLK_SSI_ALL 5 132 #define R8A7790_CLK_SSI9 6 133 #define R8A7790_CLK_SSI8 7 134 #define R8A7790_CLK_SSI7 8 135 #define R8A7790_CLK_SSI6 9 136 #define R8A7790_CLK_SSI5 10 137 #define R8A7790_CLK_SSI4 11 138 #define R8A7790_CLK_SSI3 12 139 #define R8A7790_CLK_SSI2 13 140 #define R8A7790_CLK_SSI1 14 141 #define R8A7790_CLK_SSI0 15 142 #define R8A7790_CLK_SCU_ALL 17 143 #define R8A7790_CLK_SCU_DVC1 18 144 #define R8A7790_CLK_SCU_DVC0 19 145 #define R8A7790_CLK_SCU_CTU1_MIX1 20 146 #define R8A7790_CLK_SCU_CTU0_MIX0 21 147 #define R8A7790_CLK_SCU_SRC9 22 148 #define R8A7790_CLK_SCU_SRC8 23 149 #define R8A7790_CLK_SCU_SRC7 24 150 #define R8A7790_CLK_SCU_SRC6 25 151 #define R8A7790_CLK_SCU_SRC5 26 152 #define R8A7790_CLK_SCU_SRC4 27 153 #define R8A7790_CLK_SCU_SRC3 28 154 #define R8A7790_CLK_SCU_SRC2 29 155 #define R8A7790_CLK_SCU_SRC1 30 156 #define R8A7790_CLK_SCU_SRC0 31 157 158 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ 159