1 /* 2 * Copyright 2013 Ideas On Board SPRL 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 */ 9 10 #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ 11 #define __DT_BINDINGS_CLOCK_R8A7790_H__ 12 13 /* CPG */ 14 #define R8A7790_CLK_MAIN 0 15 #define R8A7790_CLK_PLL0 1 16 #define R8A7790_CLK_PLL1 2 17 #define R8A7790_CLK_PLL3 3 18 #define R8A7790_CLK_LB 4 19 #define R8A7790_CLK_QSPI 5 20 #define R8A7790_CLK_SDH 6 21 #define R8A7790_CLK_SD0 7 22 #define R8A7790_CLK_SD1 8 23 #define R8A7790_CLK_Z 9 24 #define R8A7790_CLK_RCAN 10 25 #define R8A7790_CLK_ADSP 11 26 27 /* MSTP0 */ 28 #define R8A7790_CLK_MSIOF0 0 29 30 /* MSTP1 */ 31 #define R8A7790_CLK_VCP1 0 32 #define R8A7790_CLK_VCP0 1 33 #define R8A7790_CLK_VPC1 2 34 #define R8A7790_CLK_VPC0 3 35 #define R8A7790_CLK_JPU 6 36 #define R8A7790_CLK_SSP1 9 37 #define R8A7790_CLK_TMU1 11 38 #define R8A7790_CLK_3DG 12 39 #define R8A7790_CLK_2DDMAC 15 40 #define R8A7790_CLK_FDP1_2 17 41 #define R8A7790_CLK_FDP1_1 18 42 #define R8A7790_CLK_FDP1_0 19 43 #define R8A7790_CLK_TMU3 21 44 #define R8A7790_CLK_TMU2 22 45 #define R8A7790_CLK_CMT0 24 46 #define R8A7790_CLK_TMU0 25 47 #define R8A7790_CLK_VSP1_DU1 27 48 #define R8A7790_CLK_VSP1_DU0 28 49 #define R8A7790_CLK_VSP1_R 30 50 #define R8A7790_CLK_VSP1_S 31 51 52 /* MSTP2 */ 53 #define R8A7790_CLK_SCIFA2 2 54 #define R8A7790_CLK_SCIFA1 3 55 #define R8A7790_CLK_SCIFA0 4 56 #define R8A7790_CLK_MSIOF2 5 57 #define R8A7790_CLK_SCIFB0 6 58 #define R8A7790_CLK_SCIFB1 7 59 #define R8A7790_CLK_MSIOF1 8 60 #define R8A7790_CLK_MSIOF3 15 61 #define R8A7790_CLK_SCIFB2 16 62 #define R8A7790_CLK_SYS_DMAC1 18 63 #define R8A7790_CLK_SYS_DMAC0 19 64 65 /* MSTP3 */ 66 #define R8A7790_CLK_IIC2 0 67 #define R8A7790_CLK_TPU0 4 68 #define R8A7790_CLK_MMCIF1 5 69 #define R8A7790_CLK_SDHI3 11 70 #define R8A7790_CLK_SDHI2 12 71 #define R8A7790_CLK_SDHI1 13 72 #define R8A7790_CLK_SDHI0 14 73 #define R8A7790_CLK_MMCIF0 15 74 #define R8A7790_CLK_IIC0 18 75 #define R8A7790_CLK_PCIEC 19 76 #define R8A7790_CLK_IIC1 23 77 #define R8A7790_CLK_SSUSB 28 78 #define R8A7790_CLK_CMT1 29 79 #define R8A7790_CLK_USBDMAC0 30 80 #define R8A7790_CLK_USBDMAC1 31 81 82 /* MSTP4 */ 83 #define R8A7790_CLK_IRQC 7 84 85 /* MSTP5 */ 86 #define R8A7790_CLK_AUDIO_DMAC1 1 87 #define R8A7790_CLK_AUDIO_DMAC0 2 88 #define R8A7790_CLK_ADSP_MOD 6 89 #define R8A7790_CLK_THERMAL 22 90 #define R8A7790_CLK_PWM 23 91 92 /* MSTP7 */ 93 #define R8A7790_CLK_EHCI 3 94 #define R8A7790_CLK_HSUSB 4 95 #define R8A7790_CLK_HSCIF1 16 96 #define R8A7790_CLK_HSCIF0 17 97 #define R8A7790_CLK_SCIF1 20 98 #define R8A7790_CLK_SCIF0 21 99 #define R8A7790_CLK_DU2 22 100 #define R8A7790_CLK_DU1 23 101 #define R8A7790_CLK_DU0 24 102 #define R8A7790_CLK_LVDS1 25 103 #define R8A7790_CLK_LVDS0 26 104 105 /* MSTP8 */ 106 #define R8A7790_CLK_MLB 2 107 #define R8A7790_CLK_VIN3 8 108 #define R8A7790_CLK_VIN2 9 109 #define R8A7790_CLK_VIN1 10 110 #define R8A7790_CLK_VIN0 11 111 #define R8A7790_CLK_ETHER 13 112 #define R8A7790_CLK_SATA1 14 113 #define R8A7790_CLK_SATA0 15 114 115 /* MSTP9 */ 116 #define R8A7790_CLK_GPIO5 7 117 #define R8A7790_CLK_GPIO4 8 118 #define R8A7790_CLK_GPIO3 9 119 #define R8A7790_CLK_GPIO2 10 120 #define R8A7790_CLK_GPIO1 11 121 #define R8A7790_CLK_GPIO0 12 122 #define R8A7790_CLK_RCAN1 15 123 #define R8A7790_CLK_RCAN0 16 124 #define R8A7790_CLK_QSPI_MOD 17 125 #define R8A7790_CLK_IICDVFS 26 126 #define R8A7790_CLK_I2C3 28 127 #define R8A7790_CLK_I2C2 29 128 #define R8A7790_CLK_I2C1 30 129 #define R8A7790_CLK_I2C0 31 130 131 /* MSTP10 */ 132 #define R8A7790_CLK_SSI_ALL 5 133 #define R8A7790_CLK_SSI9 6 134 #define R8A7790_CLK_SSI8 7 135 #define R8A7790_CLK_SSI7 8 136 #define R8A7790_CLK_SSI6 9 137 #define R8A7790_CLK_SSI5 10 138 #define R8A7790_CLK_SSI4 11 139 #define R8A7790_CLK_SSI3 12 140 #define R8A7790_CLK_SSI2 13 141 #define R8A7790_CLK_SSI1 14 142 #define R8A7790_CLK_SSI0 15 143 #define R8A7790_CLK_SCU_ALL 17 144 #define R8A7790_CLK_SCU_DVC1 18 145 #define R8A7790_CLK_SCU_DVC0 19 146 #define R8A7790_CLK_SCU_SRC9 22 147 #define R8A7790_CLK_SCU_SRC8 23 148 #define R8A7790_CLK_SCU_SRC7 24 149 #define R8A7790_CLK_SCU_SRC6 25 150 #define R8A7790_CLK_SCU_SRC5 26 151 #define R8A7790_CLK_SCU_SRC4 27 152 #define R8A7790_CLK_SCU_SRC3 28 153 #define R8A7790_CLK_SCU_SRC2 29 154 #define R8A7790_CLK_SCU_SRC1 30 155 #define R8A7790_CLK_SCU_SRC0 31 156 157 #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */ 158