154ce17ddSBiju Das /* SPDX-License-Identifier: GPL-2.0 254ce17ddSBiju Das * 354ce17ddSBiju Das * Copyright (C) 2019 Renesas Electronics Corp. 454ce17ddSBiju Das */ 554ce17ddSBiju Das #ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ 654ce17ddSBiju Das #define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ 754ce17ddSBiju Das 854ce17ddSBiju Das #include <dt-bindings/clock/renesas-cpg-mssr.h> 954ce17ddSBiju Das 1054ce17ddSBiju Das /* r8a774b1 CPG Core Clocks */ 1154ce17ddSBiju Das #define R8A774B1_CLK_Z 0 1254ce17ddSBiju Das #define R8A774B1_CLK_ZG 1 1354ce17ddSBiju Das #define R8A774B1_CLK_ZTR 2 1454ce17ddSBiju Das #define R8A774B1_CLK_ZTRD2 3 1554ce17ddSBiju Das #define R8A774B1_CLK_ZT 4 1654ce17ddSBiju Das #define R8A774B1_CLK_ZX 5 1754ce17ddSBiju Das #define R8A774B1_CLK_S0D1 6 1854ce17ddSBiju Das #define R8A774B1_CLK_S0D2 7 1954ce17ddSBiju Das #define R8A774B1_CLK_S0D3 8 2054ce17ddSBiju Das #define R8A774B1_CLK_S0D4 9 2154ce17ddSBiju Das #define R8A774B1_CLK_S0D6 10 2254ce17ddSBiju Das #define R8A774B1_CLK_S0D8 11 2354ce17ddSBiju Das #define R8A774B1_CLK_S0D12 12 2454ce17ddSBiju Das #define R8A774B1_CLK_S1D2 13 2554ce17ddSBiju Das #define R8A774B1_CLK_S1D4 14 2654ce17ddSBiju Das #define R8A774B1_CLK_S2D1 15 2754ce17ddSBiju Das #define R8A774B1_CLK_S2D2 16 2854ce17ddSBiju Das #define R8A774B1_CLK_S2D4 17 2954ce17ddSBiju Das #define R8A774B1_CLK_S3D1 18 3054ce17ddSBiju Das #define R8A774B1_CLK_S3D2 19 3154ce17ddSBiju Das #define R8A774B1_CLK_S3D4 20 3254ce17ddSBiju Das #define R8A774B1_CLK_LB 21 3354ce17ddSBiju Das #define R8A774B1_CLK_CL 22 3454ce17ddSBiju Das #define R8A774B1_CLK_ZB3 23 3554ce17ddSBiju Das #define R8A774B1_CLK_ZB3D2 24 3654ce17ddSBiju Das #define R8A774B1_CLK_CR 25 3754ce17ddSBiju Das #define R8A774B1_CLK_DDR 26 3854ce17ddSBiju Das #define R8A774B1_CLK_SD0H 27 3954ce17ddSBiju Das #define R8A774B1_CLK_SD0 28 4054ce17ddSBiju Das #define R8A774B1_CLK_SD1H 29 4154ce17ddSBiju Das #define R8A774B1_CLK_SD1 30 4254ce17ddSBiju Das #define R8A774B1_CLK_SD2H 31 4354ce17ddSBiju Das #define R8A774B1_CLK_SD2 32 4454ce17ddSBiju Das #define R8A774B1_CLK_SD3H 33 4554ce17ddSBiju Das #define R8A774B1_CLK_SD3 34 4654ce17ddSBiju Das #define R8A774B1_CLK_RPC 35 4754ce17ddSBiju Das #define R8A774B1_CLK_RPCD2 36 4854ce17ddSBiju Das #define R8A774B1_CLK_MSO 37 4954ce17ddSBiju Das #define R8A774B1_CLK_HDMI 38 5054ce17ddSBiju Das #define R8A774B1_CLK_CSI0 39 5154ce17ddSBiju Das #define R8A774B1_CLK_CP 40 5254ce17ddSBiju Das #define R8A774B1_CLK_CPEX 41 5354ce17ddSBiju Das #define R8A774B1_CLK_R 42 5454ce17ddSBiju Das #define R8A774B1_CLK_OSC 43 5554ce17ddSBiju Das #define R8A774B1_CLK_CANFD 44 5654ce17ddSBiju Das 5754ce17ddSBiju Das #endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ 58