141b2df22SLad Prabhakar /* SPDX-License-Identifier: GPL-2.0+
241b2df22SLad Prabhakar  *
341b2df22SLad Prabhakar  * Copyright (C) 2020 Renesas Electronics Corp.
441b2df22SLad Prabhakar  */
541b2df22SLad Prabhakar #ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
641b2df22SLad Prabhakar #define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__
741b2df22SLad Prabhakar 
841b2df22SLad Prabhakar #include <dt-bindings/clock/renesas-cpg-mssr.h>
941b2df22SLad Prabhakar 
1041b2df22SLad Prabhakar /* r8a7742 CPG Core Clocks */
1141b2df22SLad Prabhakar #define R8A7742_CLK_Z		0
1241b2df22SLad Prabhakar #define R8A7742_CLK_Z2		1
1341b2df22SLad Prabhakar #define R8A7742_CLK_ZG		2
1441b2df22SLad Prabhakar #define R8A7742_CLK_ZTR		3
1541b2df22SLad Prabhakar #define R8A7742_CLK_ZTRD2	4
1641b2df22SLad Prabhakar #define R8A7742_CLK_ZT		5
1741b2df22SLad Prabhakar #define R8A7742_CLK_ZX		6
1841b2df22SLad Prabhakar #define R8A7742_CLK_ZS		7
1941b2df22SLad Prabhakar #define R8A7742_CLK_HP		8
2041b2df22SLad Prabhakar #define R8A7742_CLK_B		9
2141b2df22SLad Prabhakar #define R8A7742_CLK_LB		10
2241b2df22SLad Prabhakar #define R8A7742_CLK_P		11
2341b2df22SLad Prabhakar #define R8A7742_CLK_CL		12
2441b2df22SLad Prabhakar #define R8A7742_CLK_M2		13
2541b2df22SLad Prabhakar #define R8A7742_CLK_ZB3		14
2641b2df22SLad Prabhakar #define R8A7742_CLK_ZB3D2	15
2741b2df22SLad Prabhakar #define R8A7742_CLK_DDR		16
2841b2df22SLad Prabhakar #define R8A7742_CLK_SDH		17
2941b2df22SLad Prabhakar #define R8A7742_CLK_SD0		18
3041b2df22SLad Prabhakar #define R8A7742_CLK_SD1		19
3141b2df22SLad Prabhakar #define R8A7742_CLK_SD2		20
3241b2df22SLad Prabhakar #define R8A7742_CLK_SD3		21
3341b2df22SLad Prabhakar #define R8A7742_CLK_MMC0	22
3441b2df22SLad Prabhakar #define R8A7742_CLK_MMC1	23
3541b2df22SLad Prabhakar #define R8A7742_CLK_MP		24
3641b2df22SLad Prabhakar #define R8A7742_CLK_QSPI	25
3741b2df22SLad Prabhakar #define R8A7742_CLK_CP		26
3841b2df22SLad Prabhakar #define R8A7742_CLK_RCAN	27
3941b2df22SLad Prabhakar #define R8A7742_CLK_R		28
4041b2df22SLad Prabhakar #define R8A7742_CLK_OSC		29
4141b2df22SLad Prabhakar 
4241b2df22SLad Prabhakar #endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */
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