12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
2477fa2bcSUlrich Hecht /*
3477fa2bcSUlrich Hecht  * Copyright 2014 Ulrich Hecht
4477fa2bcSUlrich Hecht  */
5477fa2bcSUlrich Hecht 
6477fa2bcSUlrich Hecht #ifndef __DT_BINDINGS_CLOCK_R8A7740_H__
7477fa2bcSUlrich Hecht #define __DT_BINDINGS_CLOCK_R8A7740_H__
8477fa2bcSUlrich Hecht 
9477fa2bcSUlrich Hecht /* CPG */
10477fa2bcSUlrich Hecht #define R8A7740_CLK_SYSTEM	0
11477fa2bcSUlrich Hecht #define R8A7740_CLK_PLLC0	1
12477fa2bcSUlrich Hecht #define R8A7740_CLK_PLLC1	2
13477fa2bcSUlrich Hecht #define R8A7740_CLK_PLLC2	3
14477fa2bcSUlrich Hecht #define R8A7740_CLK_R		4
15477fa2bcSUlrich Hecht #define R8A7740_CLK_USB24S	5
16477fa2bcSUlrich Hecht #define R8A7740_CLK_I		6
17477fa2bcSUlrich Hecht #define R8A7740_CLK_ZG		7
18477fa2bcSUlrich Hecht #define R8A7740_CLK_B		8
19477fa2bcSUlrich Hecht #define R8A7740_CLK_M1		9
20477fa2bcSUlrich Hecht #define R8A7740_CLK_HP		10
21477fa2bcSUlrich Hecht #define R8A7740_CLK_HPP		11
22477fa2bcSUlrich Hecht #define R8A7740_CLK_USBP	12
23477fa2bcSUlrich Hecht #define R8A7740_CLK_S		13
24477fa2bcSUlrich Hecht #define R8A7740_CLK_ZB		14
25477fa2bcSUlrich Hecht #define R8A7740_CLK_M3		15
26477fa2bcSUlrich Hecht #define R8A7740_CLK_CP		16
27477fa2bcSUlrich Hecht 
28477fa2bcSUlrich Hecht /* MSTP1 */
29477fa2bcSUlrich Hecht #define R8A7740_CLK_CEU21	28
30477fa2bcSUlrich Hecht #define R8A7740_CLK_CEU20	27
31477fa2bcSUlrich Hecht #define R8A7740_CLK_TMU0	25
32477fa2bcSUlrich Hecht #define R8A7740_CLK_LCDC1	17
33477fa2bcSUlrich Hecht #define R8A7740_CLK_IIC0	16
34477fa2bcSUlrich Hecht #define R8A7740_CLK_TMU1	11
35477fa2bcSUlrich Hecht #define R8A7740_CLK_LCDC0	0
36477fa2bcSUlrich Hecht 
37477fa2bcSUlrich Hecht /* MSTP2 */
38477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFA6	30
393ab84ee9SGeert Uytterhoeven #define R8A7740_CLK_INTCA	29
40477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFA7	22
41477fa2bcSUlrich Hecht #define R8A7740_CLK_DMAC1	18
42477fa2bcSUlrich Hecht #define R8A7740_CLK_DMAC2	17
43477fa2bcSUlrich Hecht #define R8A7740_CLK_DMAC3	16
44477fa2bcSUlrich Hecht #define R8A7740_CLK_USBDMAC	14
45477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFA5	7
46477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFB	6
47477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFA0	4
48477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFA1	3
49477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFA2	2
50477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFA3	1
51477fa2bcSUlrich Hecht #define R8A7740_CLK_SCIFA4	0
52477fa2bcSUlrich Hecht 
53477fa2bcSUlrich Hecht /* MSTP3 */
54477fa2bcSUlrich Hecht #define R8A7740_CLK_CMT1	29
55477fa2bcSUlrich Hecht #define R8A7740_CLK_FSI		28
56477fa2bcSUlrich Hecht #define R8A7740_CLK_IIC1	23
57477fa2bcSUlrich Hecht #define R8A7740_CLK_USBF	20
58477fa2bcSUlrich Hecht #define R8A7740_CLK_SDHI0	14
59477fa2bcSUlrich Hecht #define R8A7740_CLK_SDHI1	13
60477fa2bcSUlrich Hecht #define R8A7740_CLK_MMC		12
61477fa2bcSUlrich Hecht #define R8A7740_CLK_GETHER	9
62477fa2bcSUlrich Hecht #define R8A7740_CLK_TPU0	4
63477fa2bcSUlrich Hecht 
64477fa2bcSUlrich Hecht /* MSTP4 */
65477fa2bcSUlrich Hecht #define R8A7740_CLK_USBH	16
66477fa2bcSUlrich Hecht #define R8A7740_CLK_SDHI2	15
67477fa2bcSUlrich Hecht #define R8A7740_CLK_USBFUNC	7
68477fa2bcSUlrich Hecht #define R8A7740_CLK_USBPHY	6
69477fa2bcSUlrich Hecht 
70477fa2bcSUlrich Hecht /* SUBCK* */
71477fa2bcSUlrich Hecht #define R8A7740_CLK_SUBCK	9
72477fa2bcSUlrich Hecht #define R8A7740_CLK_SUBCK2	10
73477fa2bcSUlrich Hecht 
74477fa2bcSUlrich Hecht #endif /* __DT_BINDINGS_CLOCK_R8A7740_H__ */
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