1fde35c9cSChris Brandt /* SPDX-License-Identifier: GPL-2.0 2fde35c9cSChris Brandt * 3fde35c9cSChris Brandt * Copyright (C) 2018 Renesas Electronics Corp. 4fde35c9cSChris Brandt * 5fde35c9cSChris Brandt */ 6fde35c9cSChris Brandt 7fde35c9cSChris Brandt #ifndef __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ 8fde35c9cSChris Brandt #define __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ 9fde35c9cSChris Brandt 10fde35c9cSChris Brandt #include <dt-bindings/clock/renesas-cpg-mssr.h> 11fde35c9cSChris Brandt 12fde35c9cSChris Brandt /* R7S9210 CPG Core Clocks */ 13fde35c9cSChris Brandt #define R7S9210_CLK_I 0 14fde35c9cSChris Brandt #define R7S9210_CLK_G 1 15fde35c9cSChris Brandt #define R7S9210_CLK_B 2 16fde35c9cSChris Brandt #define R7S9210_CLK_P1 3 17fde35c9cSChris Brandt #define R7S9210_CLK_P1C 4 18fde35c9cSChris Brandt #define R7S9210_CLK_P0 5 19fde35c9cSChris Brandt 20fde35c9cSChris Brandt #endif /* __DT_BINDINGS_CLOCK_R7S9210_CPG_MSSR_H__ */ 21