1 /*
2  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3  *
4  * This software is licensed under the terms of the GNU General Public
5  * License version 2, as published by the Free Software Foundation, and
6  * may be copied, distributed, and modified under those terms.
7  *
8  * This program is distributed in the hope that it will be useful,
9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8974_H
15 #define _DT_BINDINGS_CLK_MSM_GCC_8974_H
16 
17 #define GPLL0							0
18 #define GPLL0_VOTE						1
19 #define CONFIG_NOC_CLK_SRC					2
20 #define GPLL2							3
21 #define GPLL2_VOTE						4
22 #define GPLL3							5
23 #define GPLL3_VOTE						6
24 #define PERIPH_NOC_CLK_SRC					7
25 #define BLSP_UART_SIM_CLK_SRC					8
26 #define QDSS_TSCTR_CLK_SRC					9
27 #define BIMC_DDR_CLK_SRC					10
28 #define SYSTEM_NOC_CLK_SRC					11
29 #define GPLL1							12
30 #define GPLL1_VOTE						13
31 #define RPM_CLK_SRC						14
32 #define GCC_BIMC_CLK						15
33 #define BIMC_DDR_CPLL0_ROOT_CLK_SRC				16
34 #define KPSS_AHB_CLK_SRC					17
35 #define QDSS_AT_CLK_SRC						18
36 #define USB30_MASTER_CLK_SRC					19
37 #define BIMC_DDR_CPLL1_ROOT_CLK_SRC				20
38 #define QDSS_STM_CLK_SRC					21
39 #define ACC_CLK_SRC						22
40 #define SEC_CTRL_CLK_SRC					23
41 #define BLSP1_QUP1_I2C_APPS_CLK_SRC				24
42 #define BLSP1_QUP1_SPI_APPS_CLK_SRC				25
43 #define BLSP1_QUP2_I2C_APPS_CLK_SRC				26
44 #define BLSP1_QUP2_SPI_APPS_CLK_SRC				27
45 #define BLSP1_QUP3_I2C_APPS_CLK_SRC				28
46 #define BLSP1_QUP3_SPI_APPS_CLK_SRC				29
47 #define BLSP1_QUP4_I2C_APPS_CLK_SRC				30
48 #define BLSP1_QUP4_SPI_APPS_CLK_SRC				31
49 #define BLSP1_QUP5_I2C_APPS_CLK_SRC				32
50 #define BLSP1_QUP5_SPI_APPS_CLK_SRC				33
51 #define BLSP1_QUP6_I2C_APPS_CLK_SRC				34
52 #define BLSP1_QUP6_SPI_APPS_CLK_SRC				35
53 #define BLSP1_UART1_APPS_CLK_SRC				36
54 #define BLSP1_UART2_APPS_CLK_SRC				37
55 #define BLSP1_UART3_APPS_CLK_SRC				38
56 #define BLSP1_UART4_APPS_CLK_SRC				39
57 #define BLSP1_UART5_APPS_CLK_SRC				40
58 #define BLSP1_UART6_APPS_CLK_SRC				41
59 #define BLSP2_QUP1_I2C_APPS_CLK_SRC				42
60 #define BLSP2_QUP1_SPI_APPS_CLK_SRC				43
61 #define BLSP2_QUP2_I2C_APPS_CLK_SRC				44
62 #define BLSP2_QUP2_SPI_APPS_CLK_SRC				45
63 #define BLSP2_QUP3_I2C_APPS_CLK_SRC				46
64 #define BLSP2_QUP3_SPI_APPS_CLK_SRC				47
65 #define BLSP2_QUP4_I2C_APPS_CLK_SRC				48
66 #define BLSP2_QUP4_SPI_APPS_CLK_SRC				49
67 #define BLSP2_QUP5_I2C_APPS_CLK_SRC				50
68 #define BLSP2_QUP5_SPI_APPS_CLK_SRC				51
69 #define BLSP2_QUP6_I2C_APPS_CLK_SRC				52
70 #define BLSP2_QUP6_SPI_APPS_CLK_SRC				53
71 #define BLSP2_UART1_APPS_CLK_SRC				54
72 #define BLSP2_UART2_APPS_CLK_SRC				55
73 #define BLSP2_UART3_APPS_CLK_SRC				56
74 #define BLSP2_UART4_APPS_CLK_SRC				57
75 #define BLSP2_UART5_APPS_CLK_SRC				58
76 #define BLSP2_UART6_APPS_CLK_SRC				59
77 #define CE1_CLK_SRC						60
78 #define CE2_CLK_SRC						61
79 #define GP1_CLK_SRC						62
80 #define GP2_CLK_SRC						63
81 #define GP3_CLK_SRC						64
82 #define PDM2_CLK_SRC						65
83 #define QDSS_TRACECLKIN_CLK_SRC					66
84 #define RBCPR_CLK_SRC						67
85 #define SDCC1_APPS_CLK_SRC					68
86 #define SDCC2_APPS_CLK_SRC					69
87 #define SDCC3_APPS_CLK_SRC					70
88 #define SDCC4_APPS_CLK_SRC					71
89 #define SPMI_AHB_CLK_SRC					72
90 #define SPMI_SER_CLK_SRC					73
91 #define TSIF_REF_CLK_SRC					74
92 #define USB30_MOCK_UTMI_CLK_SRC					75
93 #define USB_HS_SYSTEM_CLK_SRC					76
94 #define USB_HSIC_CLK_SRC					77
95 #define USB_HSIC_IO_CAL_CLK_SRC					78
96 #define USB_HSIC_SYSTEM_CLK_SRC					79
97 #define GCC_BAM_DMA_AHB_CLK					80
98 #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK			81
99 #define GCC_BIMC_CFG_AHB_CLK					82
100 #define GCC_BIMC_KPSS_AXI_CLK					83
101 #define GCC_BIMC_SLEEP_CLK					84
102 #define GCC_BIMC_SYSNOC_AXI_CLK					85
103 #define GCC_BIMC_XO_CLK						86
104 #define GCC_BLSP1_AHB_CLK					87
105 #define GCC_BLSP1_SLEEP_CLK					88
106 #define GCC_BLSP1_QUP1_I2C_APPS_CLK				89
107 #define GCC_BLSP1_QUP1_SPI_APPS_CLK				90
108 #define GCC_BLSP1_QUP2_I2C_APPS_CLK				91
109 #define GCC_BLSP1_QUP2_SPI_APPS_CLK				92
110 #define GCC_BLSP1_QUP3_I2C_APPS_CLK				93
111 #define GCC_BLSP1_QUP3_SPI_APPS_CLK				94
112 #define GCC_BLSP1_QUP4_I2C_APPS_CLK				95
113 #define GCC_BLSP1_QUP4_SPI_APPS_CLK				96
114 #define GCC_BLSP1_QUP5_I2C_APPS_CLK				97
115 #define GCC_BLSP1_QUP5_SPI_APPS_CLK				98
116 #define GCC_BLSP1_QUP6_I2C_APPS_CLK				99
117 #define GCC_BLSP1_QUP6_SPI_APPS_CLK				100
118 #define GCC_BLSP1_UART1_APPS_CLK				101
119 #define GCC_BLSP1_UART1_SIM_CLK					102
120 #define GCC_BLSP1_UART2_APPS_CLK				103
121 #define GCC_BLSP1_UART2_SIM_CLK					104
122 #define GCC_BLSP1_UART3_APPS_CLK				105
123 #define GCC_BLSP1_UART3_SIM_CLK					106
124 #define GCC_BLSP1_UART4_APPS_CLK				107
125 #define GCC_BLSP1_UART4_SIM_CLK					108
126 #define GCC_BLSP1_UART5_APPS_CLK				109
127 #define GCC_BLSP1_UART5_SIM_CLK					110
128 #define GCC_BLSP1_UART6_APPS_CLK				111
129 #define GCC_BLSP1_UART6_SIM_CLK					112
130 #define GCC_BLSP2_AHB_CLK					113
131 #define GCC_BLSP2_SLEEP_CLK					114
132 #define GCC_BLSP2_QUP1_I2C_APPS_CLK				115
133 #define GCC_BLSP2_QUP1_SPI_APPS_CLK				116
134 #define GCC_BLSP2_QUP2_I2C_APPS_CLK				117
135 #define GCC_BLSP2_QUP2_SPI_APPS_CLK				118
136 #define GCC_BLSP2_QUP3_I2C_APPS_CLK				119
137 #define GCC_BLSP2_QUP3_SPI_APPS_CLK				120
138 #define GCC_BLSP2_QUP4_I2C_APPS_CLK				121
139 #define GCC_BLSP2_QUP4_SPI_APPS_CLK				122
140 #define GCC_BLSP2_QUP5_I2C_APPS_CLK				123
141 #define GCC_BLSP2_QUP5_SPI_APPS_CLK				124
142 #define GCC_BLSP2_QUP6_I2C_APPS_CLK				125
143 #define GCC_BLSP2_QUP6_SPI_APPS_CLK				126
144 #define GCC_BLSP2_UART1_APPS_CLK				127
145 #define GCC_BLSP2_UART1_SIM_CLK					128
146 #define GCC_BLSP2_UART2_APPS_CLK				129
147 #define GCC_BLSP2_UART2_SIM_CLK					130
148 #define GCC_BLSP2_UART3_APPS_CLK				131
149 #define GCC_BLSP2_UART3_SIM_CLK					132
150 #define GCC_BLSP2_UART4_APPS_CLK				133
151 #define GCC_BLSP2_UART4_SIM_CLK					134
152 #define GCC_BLSP2_UART5_APPS_CLK				135
153 #define GCC_BLSP2_UART5_SIM_CLK					136
154 #define GCC_BLSP2_UART6_APPS_CLK				137
155 #define GCC_BLSP2_UART6_SIM_CLK					138
156 #define GCC_BOOT_ROM_AHB_CLK					139
157 #define GCC_CE1_AHB_CLK						140
158 #define GCC_CE1_AXI_CLK						141
159 #define GCC_CE1_CLK						142
160 #define GCC_CE2_AHB_CLK						143
161 #define GCC_CE2_AXI_CLK						144
162 #define GCC_CE2_CLK						145
163 #define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK				146
164 #define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK				147
165 #define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK				148
166 #define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK				149
167 #define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK				150
168 #define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK				151
169 #define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK				152
170 #define GCC_CFG_NOC_AHB_CLK					153
171 #define GCC_CFG_NOC_DDR_CFG_CLK					154
172 #define GCC_CFG_NOC_RPM_AHB_CLK					155
173 #define GCC_BIMC_DDR_CPLL0_CLK					156
174 #define GCC_BIMC_DDR_CPLL1_CLK					157
175 #define GCC_DDR_DIM_CFG_CLK					158
176 #define GCC_DDR_DIM_SLEEP_CLK					159
177 #define GCC_DEHR_CLK						160
178 #define GCC_AHB_CLK						161
179 #define GCC_IM_SLEEP_CLK					162
180 #define GCC_XO_CLK						163
181 #define GCC_XO_DIV4_CLK						164
182 #define GCC_GP1_CLK						165
183 #define GCC_GP2_CLK						166
184 #define GCC_GP3_CLK						167
185 #define GCC_IMEM_AXI_CLK					168
186 #define GCC_IMEM_CFG_AHB_CLK					169
187 #define GCC_KPSS_AHB_CLK					170
188 #define GCC_KPSS_AXI_CLK					171
189 #define GCC_LPASS_Q6_AXI_CLK					172
190 #define GCC_MMSS_NOC_AT_CLK					173
191 #define GCC_MMSS_NOC_CFG_AHB_CLK				174
192 #define GCC_OCMEM_NOC_CFG_AHB_CLK				175
193 #define GCC_OCMEM_SYS_NOC_AXI_CLK				176
194 #define GCC_MPM_AHB_CLK						177
195 #define GCC_MSG_RAM_AHB_CLK					178
196 #define GCC_MSS_CFG_AHB_CLK					179
197 #define GCC_MSS_Q6_BIMC_AXI_CLK					180
198 #define GCC_NOC_CONF_XPU_AHB_CLK				181
199 #define GCC_PDM2_CLK						182
200 #define GCC_PDM_AHB_CLK						183
201 #define GCC_PDM_XO4_CLK						184
202 #define GCC_PERIPH_NOC_AHB_CLK					185
203 #define GCC_PERIPH_NOC_AT_CLK					186
204 #define GCC_PERIPH_NOC_CFG_AHB_CLK				187
205 #define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK				188
206 #define GCC_PERIPH_XPU_AHB_CLK					189
207 #define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK				190
208 #define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK				191
209 #define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK				192
210 #define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK				193
211 #define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK				194
212 #define GCC_PRNG_AHB_CLK					195
213 #define GCC_QDSS_AT_CLK						196
214 #define GCC_QDSS_CFG_AHB_CLK					197
215 #define GCC_QDSS_DAP_AHB_CLK					198
216 #define GCC_QDSS_DAP_CLK					199
217 #define GCC_QDSS_ETR_USB_CLK					200
218 #define GCC_QDSS_STM_CLK					201
219 #define GCC_QDSS_TRACECLKIN_CLK					202
220 #define GCC_QDSS_TSCTR_DIV16_CLK				203
221 #define GCC_QDSS_TSCTR_DIV2_CLK					204
222 #define GCC_QDSS_TSCTR_DIV3_CLK					205
223 #define GCC_QDSS_TSCTR_DIV4_CLK					206
224 #define GCC_QDSS_TSCTR_DIV8_CLK					207
225 #define GCC_QDSS_RBCPR_XPU_AHB_CLK				208
226 #define GCC_RBCPR_AHB_CLK					209
227 #define GCC_RBCPR_CLK						210
228 #define GCC_RPM_BUS_AHB_CLK					211
229 #define GCC_RPM_PROC_HCLK					212
230 #define GCC_RPM_SLEEP_CLK					213
231 #define GCC_RPM_TIMER_CLK					214
232 #define GCC_SDCC1_AHB_CLK					215
233 #define GCC_SDCC1_APPS_CLK					216
234 #define GCC_SDCC1_INACTIVITY_TIMERS_CLK				217
235 #define GCC_SDCC2_AHB_CLK					218
236 #define GCC_SDCC2_APPS_CLK					219
237 #define GCC_SDCC2_INACTIVITY_TIMERS_CLK				220
238 #define GCC_SDCC3_AHB_CLK					221
239 #define GCC_SDCC3_APPS_CLK					222
240 #define GCC_SDCC3_INACTIVITY_TIMERS_CLK				223
241 #define GCC_SDCC4_AHB_CLK					224
242 #define GCC_SDCC4_APPS_CLK					225
243 #define GCC_SDCC4_INACTIVITY_TIMERS_CLK				226
244 #define GCC_SEC_CTRL_ACC_CLK					227
245 #define GCC_SEC_CTRL_AHB_CLK					228
246 #define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK				229
247 #define GCC_SEC_CTRL_CLK					230
248 #define GCC_SEC_CTRL_SENSE_CLK					231
249 #define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK				232
250 #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK				233
251 #define GCC_SPDM_BIMC_CY_CLK					234
252 #define GCC_SPDM_CFG_AHB_CLK					235
253 #define GCC_SPDM_DEBUG_CY_CLK					236
254 #define GCC_SPDM_FF_CLK						237
255 #define GCC_SPDM_MSTR_AHB_CLK					238
256 #define GCC_SPDM_PNOC_CY_CLK					239
257 #define GCC_SPDM_RPM_CY_CLK					240
258 #define GCC_SPDM_SNOC_CY_CLK					241
259 #define GCC_SPMI_AHB_CLK					242
260 #define GCC_SPMI_CNOC_AHB_CLK					243
261 #define GCC_SPMI_SER_CLK					244
262 #define GCC_SNOC_CNOC_AHB_CLK					245
263 #define GCC_SNOC_PNOC_AHB_CLK					246
264 #define GCC_SYS_NOC_AT_CLK					247
265 #define GCC_SYS_NOC_AXI_CLK					248
266 #define GCC_SYS_NOC_KPSS_AHB_CLK				249
267 #define GCC_SYS_NOC_QDSS_STM_AXI_CLK				250
268 #define GCC_SYS_NOC_USB3_AXI_CLK				251
269 #define GCC_TCSR_AHB_CLK					252
270 #define GCC_TLMM_AHB_CLK					253
271 #define GCC_TLMM_CLK						254
272 #define GCC_TSIF_AHB_CLK					255
273 #define GCC_TSIF_INACTIVITY_TIMERS_CLK				256
274 #define GCC_TSIF_REF_CLK					257
275 #define GCC_USB2A_PHY_SLEEP_CLK					258
276 #define GCC_USB2B_PHY_SLEEP_CLK					259
277 #define GCC_USB30_MASTER_CLK					260
278 #define GCC_USB30_MOCK_UTMI_CLK					261
279 #define GCC_USB30_SLEEP_CLK					262
280 #define GCC_USB_HS_AHB_CLK					263
281 #define GCC_USB_HS_INACTIVITY_TIMERS_CLK			264
282 #define GCC_USB_HS_SYSTEM_CLK					265
283 #define GCC_USB_HSIC_AHB_CLK					266
284 #define GCC_USB_HSIC_CLK					267
285 #define GCC_USB_HSIC_IO_CAL_CLK					268
286 #define GCC_USB_HSIC_IO_CAL_SLEEP_CLK				269
287 #define GCC_USB_HSIC_SYSTEM_CLK					270
288 #define GCC_WCSS_GPLL1_CLK_SRC					271
289 #define GCC_MMSS_GPLL0_CLK_SRC					272
290 #define GCC_LPASS_GPLL0_CLK_SRC					273
291 #define GCC_WCSS_GPLL1_CLK_SRC_SLEEP_ENA			274
292 #define GCC_MMSS_GPLL0_CLK_SRC_SLEEP_ENA			275
293 #define GCC_LPASS_GPLL0_CLK_SRC_SLEEP_ENA			276
294 #define GCC_IMEM_AXI_CLK_SLEEP_ENA				277
295 #define GCC_SYS_NOC_KPSS_AHB_CLK_SLEEP_ENA			278
296 #define GCC_BIMC_KPSS_AXI_CLK_SLEEP_ENA				279
297 #define GCC_KPSS_AHB_CLK_SLEEP_ENA				280
298 #define GCC_KPSS_AXI_CLK_SLEEP_ENA				281
299 #define GCC_MPM_AHB_CLK_SLEEP_ENA				282
300 #define GCC_OCMEM_SYS_NOC_AXI_CLK_SLEEP_ENA			283
301 #define GCC_BLSP1_AHB_CLK_SLEEP_ENA				284
302 #define GCC_BLSP1_SLEEP_CLK_SLEEP_ENA				285
303 #define GCC_BLSP2_AHB_CLK_SLEEP_ENA				286
304 #define GCC_BLSP2_SLEEP_CLK_SLEEP_ENA				287
305 #define GCC_PRNG_AHB_CLK_SLEEP_ENA				288
306 #define GCC_BAM_DMA_AHB_CLK_SLEEP_ENA				289
307 #define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK_SLEEP_ENA		290
308 #define GCC_BOOT_ROM_AHB_CLK_SLEEP_ENA				291
309 #define GCC_MSG_RAM_AHB_CLK_SLEEP_ENA				292
310 #define GCC_TLMM_AHB_CLK_SLEEP_ENA				293
311 #define GCC_TLMM_CLK_SLEEP_ENA					294
312 #define GCC_SPMI_CNOC_AHB_CLK_SLEEP_ENA				295
313 #define GCC_CE1_CLK_SLEEP_ENA					296
314 #define GCC_CE1_AXI_CLK_SLEEP_ENA				297
315 #define GCC_CE1_AHB_CLK_SLEEP_ENA				298
316 #define GCC_CE2_CLK_SLEEP_ENA					299
317 #define GCC_CE2_AXI_CLK_SLEEP_ENA				300
318 #define GCC_CE2_AHB_CLK_SLEEP_ENA				301
319 #define GPLL4							302
320 #define GPLL4_VOTE						303
321 #define GCC_SDCC1_CDCCAL_SLEEP_CLK				304
322 #define GCC_SDCC1_CDCCAL_FF_CLK					305
323 
324 /* gdscs */
325 #define USB_HS_HSIC_GDSC					0
326 
327 #endif
328