1*a66a82f2SBjorn Andersson /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*a66a82f2SBjorn Andersson /* 3*a66a82f2SBjorn Andersson * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4*a66a82f2SBjorn Andersson * Copyright (c) 2022, Linaro Ltd. 5*a66a82f2SBjorn Andersson */ 6*a66a82f2SBjorn Andersson 7*a66a82f2SBjorn Andersson #ifndef _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H 8*a66a82f2SBjorn Andersson #define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H 9*a66a82f2SBjorn Andersson 10*a66a82f2SBjorn Andersson /* GCC clocks */ 11*a66a82f2SBjorn Andersson #define GCC_GPLL0 0 12*a66a82f2SBjorn Andersson #define GCC_GPLL0_OUT_EVEN 1 13*a66a82f2SBjorn Andersson #define GCC_GPLL2 2 14*a66a82f2SBjorn Andersson #define GCC_GPLL4 3 15*a66a82f2SBjorn Andersson #define GCC_GPLL7 4 16*a66a82f2SBjorn Andersson #define GCC_GPLL8 5 17*a66a82f2SBjorn Andersson #define GCC_GPLL9 6 18*a66a82f2SBjorn Andersson #define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7 19*a66a82f2SBjorn Andersson #define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK 8 20*a66a82f2SBjorn Andersson #define GCC_AGGRE_NOC_PCIE_4_AXI_CLK 9 21*a66a82f2SBjorn Andersson #define GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK 10 22*a66a82f2SBjorn Andersson #define GCC_AGGRE_UFS_CARD_AXI_CLK 11 23*a66a82f2SBjorn Andersson #define GCC_AGGRE_UFS_PHY_AXI_CLK 12 24*a66a82f2SBjorn Andersson #define GCC_AGGRE_USB3_MP_AXI_CLK 13 25*a66a82f2SBjorn Andersson #define GCC_AGGRE_USB3_PRIM_AXI_CLK 14 26*a66a82f2SBjorn Andersson #define GCC_AGGRE_USB3_SEC_AXI_CLK 15 27*a66a82f2SBjorn Andersson #define GCC_AGGRE_USB4_1_AXI_CLK 16 28*a66a82f2SBjorn Andersson #define GCC_AGGRE_USB4_AXI_CLK 17 29*a66a82f2SBjorn Andersson #define GCC_AGGRE_USB_NOC_AXI_CLK 18 30*a66a82f2SBjorn Andersson #define GCC_AGGRE_USB_NOC_NORTH_AXI_CLK 19 31*a66a82f2SBjorn Andersson #define GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK 20 32*a66a82f2SBjorn Andersson #define GCC_AHB2PHY0_CLK 21 33*a66a82f2SBjorn Andersson #define GCC_AHB2PHY2_CLK 22 34*a66a82f2SBjorn Andersson #define GCC_BOOT_ROM_AHB_CLK 23 35*a66a82f2SBjorn Andersson #define GCC_CAMERA_AHB_CLK 24 36*a66a82f2SBjorn Andersson #define GCC_CAMERA_HF_AXI_CLK 25 37*a66a82f2SBjorn Andersson #define GCC_CAMERA_SF_AXI_CLK 26 38*a66a82f2SBjorn Andersson #define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 27 39*a66a82f2SBjorn Andersson #define GCC_CAMERA_THROTTLE_RT_AXI_CLK 28 40*a66a82f2SBjorn Andersson #define GCC_CAMERA_THROTTLE_XO_CLK 29 41*a66a82f2SBjorn Andersson #define GCC_CAMERA_XO_CLK 30 42*a66a82f2SBjorn Andersson #define GCC_CFG_NOC_USB3_MP_AXI_CLK 31 43*a66a82f2SBjorn Andersson #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 32 44*a66a82f2SBjorn Andersson #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 33 45*a66a82f2SBjorn Andersson #define GCC_CNOC_PCIE0_TUNNEL_CLK 34 46*a66a82f2SBjorn Andersson #define GCC_CNOC_PCIE1_TUNNEL_CLK 35 47*a66a82f2SBjorn Andersson #define GCC_CNOC_PCIE4_QX_CLK 36 48*a66a82f2SBjorn Andersson #define GCC_DDRSS_GPU_AXI_CLK 37 49*a66a82f2SBjorn Andersson #define GCC_DDRSS_PCIE_SF_TBU_CLK 38 50*a66a82f2SBjorn Andersson #define GCC_DISP1_AHB_CLK 39 51*a66a82f2SBjorn Andersson #define GCC_DISP1_HF_AXI_CLK 40 52*a66a82f2SBjorn Andersson #define GCC_DISP1_SF_AXI_CLK 41 53*a66a82f2SBjorn Andersson #define GCC_DISP1_THROTTLE_NRT_AXI_CLK 42 54*a66a82f2SBjorn Andersson #define GCC_DISP1_THROTTLE_RT_AXI_CLK 43 55*a66a82f2SBjorn Andersson #define GCC_DISP1_XO_CLK 44 56*a66a82f2SBjorn Andersson #define GCC_DISP_AHB_CLK 45 57*a66a82f2SBjorn Andersson #define GCC_DISP_HF_AXI_CLK 46 58*a66a82f2SBjorn Andersson #define GCC_DISP_SF_AXI_CLK 47 59*a66a82f2SBjorn Andersson #define GCC_DISP_THROTTLE_NRT_AXI_CLK 48 60*a66a82f2SBjorn Andersson #define GCC_DISP_THROTTLE_RT_AXI_CLK 49 61*a66a82f2SBjorn Andersson #define GCC_DISP_XO_CLK 50 62*a66a82f2SBjorn Andersson #define GCC_EMAC0_AXI_CLK 51 63*a66a82f2SBjorn Andersson #define GCC_EMAC0_PTP_CLK 52 64*a66a82f2SBjorn Andersson #define GCC_EMAC0_PTP_CLK_SRC 53 65*a66a82f2SBjorn Andersson #define GCC_EMAC0_RGMII_CLK 54 66*a66a82f2SBjorn Andersson #define GCC_EMAC0_RGMII_CLK_SRC 55 67*a66a82f2SBjorn Andersson #define GCC_EMAC0_SLV_AHB_CLK 56 68*a66a82f2SBjorn Andersson #define GCC_EMAC1_AXI_CLK 57 69*a66a82f2SBjorn Andersson #define GCC_EMAC1_PTP_CLK 58 70*a66a82f2SBjorn Andersson #define GCC_EMAC1_PTP_CLK_SRC 59 71*a66a82f2SBjorn Andersson #define GCC_EMAC1_RGMII_CLK 60 72*a66a82f2SBjorn Andersson #define GCC_EMAC1_RGMII_CLK_SRC 61 73*a66a82f2SBjorn Andersson #define GCC_EMAC1_SLV_AHB_CLK 62 74*a66a82f2SBjorn Andersson #define GCC_GP1_CLK 63 75*a66a82f2SBjorn Andersson #define GCC_GP1_CLK_SRC 64 76*a66a82f2SBjorn Andersson #define GCC_GP2_CLK 65 77*a66a82f2SBjorn Andersson #define GCC_GP2_CLK_SRC 66 78*a66a82f2SBjorn Andersson #define GCC_GP3_CLK 67 79*a66a82f2SBjorn Andersson #define GCC_GP3_CLK_SRC 68 80*a66a82f2SBjorn Andersson #define GCC_GP4_CLK 69 81*a66a82f2SBjorn Andersson #define GCC_GP4_CLK_SRC 70 82*a66a82f2SBjorn Andersson #define GCC_GP5_CLK 71 83*a66a82f2SBjorn Andersson #define GCC_GP5_CLK_SRC 72 84*a66a82f2SBjorn Andersson #define GCC_GPU_CFG_AHB_CLK 73 85*a66a82f2SBjorn Andersson #define GCC_GPU_GPLL0_CLK_SRC 74 86*a66a82f2SBjorn Andersson #define GCC_GPU_GPLL0_DIV_CLK_SRC 75 87*a66a82f2SBjorn Andersson #define GCC_GPU_IREF_EN 76 88*a66a82f2SBjorn Andersson #define GCC_GPU_MEMNOC_GFX_CLK 77 89*a66a82f2SBjorn Andersson #define GCC_GPU_SNOC_DVM_GFX_CLK 78 90*a66a82f2SBjorn Andersson #define GCC_GPU_TCU_THROTTLE_AHB_CLK 79 91*a66a82f2SBjorn Andersson #define GCC_GPU_TCU_THROTTLE_CLK 80 92*a66a82f2SBjorn Andersson #define GCC_PCIE0_PHY_RCHNG_CLK 81 93*a66a82f2SBjorn Andersson #define GCC_PCIE1_PHY_RCHNG_CLK 82 94*a66a82f2SBjorn Andersson #define GCC_PCIE2A_PHY_RCHNG_CLK 83 95*a66a82f2SBjorn Andersson #define GCC_PCIE2B_PHY_RCHNG_CLK 84 96*a66a82f2SBjorn Andersson #define GCC_PCIE3A_PHY_RCHNG_CLK 85 97*a66a82f2SBjorn Andersson #define GCC_PCIE3B_PHY_RCHNG_CLK 86 98*a66a82f2SBjorn Andersson #define GCC_PCIE4_PHY_RCHNG_CLK 87 99*a66a82f2SBjorn Andersson #define GCC_PCIE_0_AUX_CLK 88 100*a66a82f2SBjorn Andersson #define GCC_PCIE_0_AUX_CLK_SRC 89 101*a66a82f2SBjorn Andersson #define GCC_PCIE_0_CFG_AHB_CLK 90 102*a66a82f2SBjorn Andersson #define GCC_PCIE_0_MSTR_AXI_CLK 91 103*a66a82f2SBjorn Andersson #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 92 104*a66a82f2SBjorn Andersson #define GCC_PCIE_0_PIPE_CLK 93 105*a66a82f2SBjorn Andersson #define GCC_PCIE_0_SLV_AXI_CLK 94 106*a66a82f2SBjorn Andersson #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95 107*a66a82f2SBjorn Andersson #define GCC_PCIE_1_AUX_CLK 96 108*a66a82f2SBjorn Andersson #define GCC_PCIE_1_AUX_CLK_SRC 97 109*a66a82f2SBjorn Andersson #define GCC_PCIE_1_CFG_AHB_CLK 98 110*a66a82f2SBjorn Andersson #define GCC_PCIE_1_MSTR_AXI_CLK 99 111*a66a82f2SBjorn Andersson #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 100 112*a66a82f2SBjorn Andersson #define GCC_PCIE_1_PIPE_CLK 101 113*a66a82f2SBjorn Andersson #define GCC_PCIE_1_SLV_AXI_CLK 102 114*a66a82f2SBjorn Andersson #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 103 115*a66a82f2SBjorn Andersson #define GCC_PCIE_2A2B_CLKREF_CLK 104 116*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_AUX_CLK 105 117*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_AUX_CLK_SRC 106 118*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_CFG_AHB_CLK 107 119*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_MSTR_AXI_CLK 108 120*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PHY_RCHNG_CLK_SRC 109 121*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PIPE_CLK 110 122*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PIPE_CLK_SRC 111 123*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PIPE_DIV_CLK_SRC 112 124*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PIPEDIV2_CLK 113 125*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_SLV_AXI_CLK 114 126*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_SLV_Q2A_AXI_CLK 115 127*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_AUX_CLK 116 128*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_AUX_CLK_SRC 117 129*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_CFG_AHB_CLK 118 130*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_MSTR_AXI_CLK 119 131*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PHY_RCHNG_CLK_SRC 120 132*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PIPE_CLK 121 133*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PIPE_CLK_SRC 122 134*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PIPE_DIV_CLK_SRC 123 135*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PIPEDIV2_CLK 124 136*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_SLV_AXI_CLK 125 137*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_SLV_Q2A_AXI_CLK 126 138*a66a82f2SBjorn Andersson #define GCC_PCIE_3A3B_CLKREF_CLK 127 139*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_AUX_CLK 128 140*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_AUX_CLK_SRC 129 141*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_CFG_AHB_CLK 130 142*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_MSTR_AXI_CLK 131 143*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 132 144*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PIPE_CLK 133 145*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PIPE_CLK_SRC 134 146*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PIPE_DIV_CLK_SRC 135 147*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PIPEDIV2_CLK 136 148*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_SLV_AXI_CLK 137 149*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 138 150*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_AUX_CLK 139 151*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_AUX_CLK_SRC 140 152*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_CFG_AHB_CLK 141 153*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_MSTR_AXI_CLK 142 154*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 143 155*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PIPE_CLK 144 156*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PIPE_CLK_SRC 145 157*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 146 158*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PIPEDIV2_CLK 147 159*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_SLV_AXI_CLK 148 160*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 149 161*a66a82f2SBjorn Andersson #define GCC_PCIE_4_AUX_CLK 150 162*a66a82f2SBjorn Andersson #define GCC_PCIE_4_AUX_CLK_SRC 151 163*a66a82f2SBjorn Andersson #define GCC_PCIE_4_CFG_AHB_CLK 152 164*a66a82f2SBjorn Andersson #define GCC_PCIE_4_CLKREF_CLK 153 165*a66a82f2SBjorn Andersson #define GCC_PCIE_4_MSTR_AXI_CLK 154 166*a66a82f2SBjorn Andersson #define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 155 167*a66a82f2SBjorn Andersson #define GCC_PCIE_4_PIPE_CLK 156 168*a66a82f2SBjorn Andersson #define GCC_PCIE_4_PIPE_CLK_SRC 157 169*a66a82f2SBjorn Andersson #define GCC_PCIE_4_PIPE_DIV_CLK_SRC 158 170*a66a82f2SBjorn Andersson #define GCC_PCIE_4_PIPEDIV2_CLK 159 171*a66a82f2SBjorn Andersson #define GCC_PCIE_4_SLV_AXI_CLK 160 172*a66a82f2SBjorn Andersson #define GCC_PCIE_4_SLV_Q2A_AXI_CLK 161 173*a66a82f2SBjorn Andersson #define GCC_PCIE_RSCC_AHB_CLK 162 174*a66a82f2SBjorn Andersson #define GCC_PCIE_RSCC_XO_CLK 163 175*a66a82f2SBjorn Andersson #define GCC_PCIE_RSCC_XO_CLK_SRC 164 176*a66a82f2SBjorn Andersson #define GCC_PCIE_THROTTLE_CFG_CLK 165 177*a66a82f2SBjorn Andersson #define GCC_PDM2_CLK 166 178*a66a82f2SBjorn Andersson #define GCC_PDM2_CLK_SRC 167 179*a66a82f2SBjorn Andersson #define GCC_PDM_AHB_CLK 168 180*a66a82f2SBjorn Andersson #define GCC_PDM_XO4_CLK 169 181*a66a82f2SBjorn Andersson #define GCC_QMIP_CAMERA_NRT_AHB_CLK 170 182*a66a82f2SBjorn Andersson #define GCC_QMIP_CAMERA_RT_AHB_CLK 171 183*a66a82f2SBjorn Andersson #define GCC_QMIP_DISP1_AHB_CLK 172 184*a66a82f2SBjorn Andersson #define GCC_QMIP_DISP1_ROT_AHB_CLK 173 185*a66a82f2SBjorn Andersson #define GCC_QMIP_DISP_AHB_CLK 174 186*a66a82f2SBjorn Andersson #define GCC_QMIP_DISP_ROT_AHB_CLK 175 187*a66a82f2SBjorn Andersson #define GCC_QMIP_VIDEO_CVP_AHB_CLK 176 188*a66a82f2SBjorn Andersson #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 177 189*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_CORE_2X_CLK 178 190*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_CORE_CLK 179 191*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_QSPI0_CLK 180 192*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S0_CLK 181 193*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S0_CLK_SRC 182 194*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S1_CLK 183 195*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S1_CLK_SRC 184 196*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S2_CLK 185 197*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S2_CLK_SRC 186 198*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S3_CLK 187 199*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S3_CLK_SRC 188 200*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S4_CLK 189 201*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S4_CLK_SRC 190 202*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC 191 203*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S5_CLK 192 204*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S5_CLK_SRC 193 205*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S6_CLK 194 206*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S6_CLK_SRC 195 207*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S7_CLK 196 208*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S7_CLK_SRC 197 209*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_CORE_2X_CLK 198 210*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_CORE_CLK 199 211*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_QSPI0_CLK 200 212*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S0_CLK 201 213*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S0_CLK_SRC 202 214*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S1_CLK 203 215*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S1_CLK_SRC 204 216*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S2_CLK 205 217*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S2_CLK_SRC 206 218*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S3_CLK 207 219*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S3_CLK_SRC 208 220*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S4_CLK 209 221*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S4_CLK_SRC 210 222*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC 211 223*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S5_CLK 212 224*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S5_CLK_SRC 213 225*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S6_CLK 214 226*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S6_CLK_SRC 215 227*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S7_CLK 216 228*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S7_CLK_SRC 217 229*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_CORE_2X_CLK 218 230*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_CORE_CLK 219 231*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_QSPI0_CLK 220 232*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S0_CLK 221 233*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S0_CLK_SRC 222 234*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S1_CLK 223 235*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S1_CLK_SRC 224 236*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S2_CLK 225 237*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S2_CLK_SRC 226 238*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S3_CLK 227 239*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S3_CLK_SRC 228 240*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S4_CLK 229 241*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S4_CLK_SRC 230 242*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC 231 243*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S5_CLK 232 244*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S5_CLK_SRC 233 245*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S6_CLK 234 246*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S6_CLK_SRC 235 247*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S7_CLK 236 248*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S7_CLK_SRC 237 249*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_0_M_AHB_CLK 238 250*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_0_S_AHB_CLK 239 251*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_1_M_AHB_CLK 240 252*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_1_S_AHB_CLK 241 253*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_2_M_AHB_CLK 242 254*a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_2_S_AHB_CLK 243 255*a66a82f2SBjorn Andersson #define GCC_SDCC2_AHB_CLK 244 256*a66a82f2SBjorn Andersson #define GCC_SDCC2_APPS_CLK 245 257*a66a82f2SBjorn Andersson #define GCC_SDCC2_APPS_CLK_SRC 246 258*a66a82f2SBjorn Andersson #define GCC_SDCC4_AHB_CLK 247 259*a66a82f2SBjorn Andersson #define GCC_SDCC4_APPS_CLK 248 260*a66a82f2SBjorn Andersson #define GCC_SDCC4_APPS_CLK_SRC 249 261*a66a82f2SBjorn Andersson #define GCC_SYS_NOC_USB_AXI_CLK 250 262*a66a82f2SBjorn Andersson #define GCC_UFS_1_CARD_CLKREF_CLK 251 263*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_AHB_CLK 252 264*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_AXI_CLK 253 265*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_AXI_CLK_SRC 254 266*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_CLKREF_CLK 255 267*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_ICE_CORE_CLK 256 268*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 257 269*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_PHY_AUX_CLK 258 270*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 259 271*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 260 272*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 261 273*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 262 274*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 263 275*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 264 276*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 265 277*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_UNIPRO_CORE_CLK 266 278*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 267 279*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_AHB_CLK 268 280*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_AXI_CLK 269 281*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_AXI_CLK_SRC 270 282*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_ICE_CORE_CLK 271 283*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 272 284*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_PHY_AUX_CLK 273 285*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 274 286*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 275 287*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 276 288*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 277 289*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 278 290*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 279 291*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 280 292*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_UNIPRO_CORE_CLK 281 293*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 282 294*a66a82f2SBjorn Andersson #define GCC_UFS_REF_CLKREF_CLK 283 295*a66a82f2SBjorn Andersson #define GCC_USB2_HS0_CLKREF_CLK 284 296*a66a82f2SBjorn Andersson #define GCC_USB2_HS1_CLKREF_CLK 285 297*a66a82f2SBjorn Andersson #define GCC_USB2_HS2_CLKREF_CLK 286 298*a66a82f2SBjorn Andersson #define GCC_USB2_HS3_CLKREF_CLK 287 299*a66a82f2SBjorn Andersson #define GCC_USB30_MP_MASTER_CLK 288 300*a66a82f2SBjorn Andersson #define GCC_USB30_MP_MASTER_CLK_SRC 289 301*a66a82f2SBjorn Andersson #define GCC_USB30_MP_MOCK_UTMI_CLK 290 302*a66a82f2SBjorn Andersson #define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 291 303*a66a82f2SBjorn Andersson #define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 292 304*a66a82f2SBjorn Andersson #define GCC_USB30_MP_SLEEP_CLK 293 305*a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MASTER_CLK 294 306*a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MASTER_CLK_SRC 295 307*a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MOCK_UTMI_CLK 296 308*a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 297 309*a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 298 310*a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_SLEEP_CLK 299 311*a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MASTER_CLK 300 312*a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MASTER_CLK_SRC 301 313*a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MOCK_UTMI_CLK 302 314*a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 303 315*a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 304 316*a66a82f2SBjorn Andersson #define GCC_USB30_SEC_SLEEP_CLK 305 317*a66a82f2SBjorn Andersson #define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 306 318*a66a82f2SBjorn Andersson #define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 307 319*a66a82f2SBjorn Andersson #define GCC_USB3_MP0_CLKREF_CLK 308 320*a66a82f2SBjorn Andersson #define GCC_USB3_MP1_CLKREF_CLK 309 321*a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_AUX_CLK 310 322*a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_AUX_CLK_SRC 311 323*a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_COM_AUX_CLK 312 324*a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_PIPE_0_CLK 313 325*a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 314 326*a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_PIPE_1_CLK 315 327*a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 316 328*a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_AUX_CLK 317 329*a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 318 330*a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 319 331*a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_PIPE_CLK 320 332*a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 321 333*a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_AUX_CLK 322 334*a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 323 335*a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_COM_AUX_CLK 324 336*a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_PIPE_CLK 325 337*a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 326 338*a66a82f2SBjorn Andersson #define GCC_USB4_1_CFG_AHB_CLK 327 339*a66a82f2SBjorn Andersson #define GCC_USB4_1_DP_CLK 328 340*a66a82f2SBjorn Andersson #define GCC_USB4_1_MASTER_CLK 329 341*a66a82f2SBjorn Andersson #define GCC_USB4_1_MASTER_CLK_SRC 330 342*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_DP_CLK_SRC 331 343*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 332 344*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 333 345*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PCIE_PIPE_CLK 334 346*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 335 347*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 336 348*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 337 349*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_RX0_CLK 338 350*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_RX0_CLK_SRC 339 351*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_RX1_CLK 340 352*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_RX1_CLK_SRC 341 353*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_SYS_CLK_SRC 342 354*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_USB_PIPE_CLK 343 355*a66a82f2SBjorn Andersson #define GCC_USB4_1_SB_IF_CLK 344 356*a66a82f2SBjorn Andersson #define GCC_USB4_1_SB_IF_CLK_SRC 345 357*a66a82f2SBjorn Andersson #define GCC_USB4_1_SYS_CLK 346 358*a66a82f2SBjorn Andersson #define GCC_USB4_1_TMU_CLK 347 359*a66a82f2SBjorn Andersson #define GCC_USB4_1_TMU_CLK_SRC 348 360*a66a82f2SBjorn Andersson #define GCC_USB4_CFG_AHB_CLK 349 361*a66a82f2SBjorn Andersson #define GCC_USB4_CLKREF_CLK 350 362*a66a82f2SBjorn Andersson #define GCC_USB4_DP_CLK 351 363*a66a82f2SBjorn Andersson #define GCC_USB4_EUD_CLKREF_CLK 352 364*a66a82f2SBjorn Andersson #define GCC_USB4_MASTER_CLK 353 365*a66a82f2SBjorn Andersson #define GCC_USB4_MASTER_CLK_SRC 354 366*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_DP_CLK_SRC 355 367*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_P2RR2P_PIPE_CLK 356 368*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC 357 369*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PCIE_PIPE_CLK 358 370*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PCIE_PIPE_CLK_SRC 359 371*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC 360 372*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC 361 373*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_RX0_CLK 362 374*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_RX0_CLK_SRC 363 375*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_RX1_CLK 364 376*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_RX1_CLK_SRC 365 377*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_SYS_CLK_SRC 366 378*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_USB_PIPE_CLK 367 379*a66a82f2SBjorn Andersson #define GCC_USB4_SB_IF_CLK 368 380*a66a82f2SBjorn Andersson #define GCC_USB4_SB_IF_CLK_SRC 369 381*a66a82f2SBjorn Andersson #define GCC_USB4_SYS_CLK 370 382*a66a82f2SBjorn Andersson #define GCC_USB4_TMU_CLK 371 383*a66a82f2SBjorn Andersson #define GCC_USB4_TMU_CLK_SRC 372 384*a66a82f2SBjorn Andersson #define GCC_VIDEO_AHB_CLK 373 385*a66a82f2SBjorn Andersson #define GCC_VIDEO_AXI0_CLK 374 386*a66a82f2SBjorn Andersson #define GCC_VIDEO_AXI1_CLK 375 387*a66a82f2SBjorn Andersson #define GCC_VIDEO_CVP_THROTTLE_CLK 376 388*a66a82f2SBjorn Andersson #define GCC_VIDEO_VCODEC_THROTTLE_CLK 377 389*a66a82f2SBjorn Andersson #define GCC_VIDEO_XO_CLK 378 390*a66a82f2SBjorn Andersson #define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 379 391*a66a82f2SBjorn Andersson #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 380 392*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_AXI_HW_CTL_CLK 381 393*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 382 394*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 383 395*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 384 396*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_AXI_HW_CTL_CLK 385 397*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 386 398*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 387 399*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 388 400*a66a82f2SBjorn Andersson 401*a66a82f2SBjorn Andersson /* GCC resets */ 402*a66a82f2SBjorn Andersson #define GCC_EMAC0_BCR 0 403*a66a82f2SBjorn Andersson #define GCC_EMAC1_BCR 1 404*a66a82f2SBjorn Andersson #define GCC_PCIE_0_LINK_DOWN_BCR 2 405*a66a82f2SBjorn Andersson #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3 406*a66a82f2SBjorn Andersson #define GCC_PCIE_0_PHY_BCR 4 407*a66a82f2SBjorn Andersson #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5 408*a66a82f2SBjorn Andersson #define GCC_PCIE_0_TUNNEL_BCR 6 409*a66a82f2SBjorn Andersson #define GCC_PCIE_1_LINK_DOWN_BCR 7 410*a66a82f2SBjorn Andersson #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8 411*a66a82f2SBjorn Andersson #define GCC_PCIE_1_PHY_BCR 9 412*a66a82f2SBjorn Andersson #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10 413*a66a82f2SBjorn Andersson #define GCC_PCIE_1_TUNNEL_BCR 11 414*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_BCR 12 415*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_LINK_DOWN_BCR 13 416*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_NOCSR_COM_PHY_BCR 14 417*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PHY_BCR 15 418*a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR 16 419*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_BCR 17 420*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_LINK_DOWN_BCR 18 421*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_NOCSR_COM_PHY_BCR 19 422*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PHY_BCR 20 423*a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR 21 424*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_BCR 22 425*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_LINK_DOWN_BCR 23 426*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 24 427*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PHY_BCR 25 428*a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 26 429*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_BCR 27 430*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_LINK_DOWN_BCR 28 431*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 29 432*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PHY_BCR 30 433*a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 31 434*a66a82f2SBjorn Andersson #define GCC_PCIE_4_BCR 32 435*a66a82f2SBjorn Andersson #define GCC_PCIE_4_LINK_DOWN_BCR 33 436*a66a82f2SBjorn Andersson #define GCC_PCIE_4_NOCSR_COM_PHY_BCR 34 437*a66a82f2SBjorn Andersson #define GCC_PCIE_4_PHY_BCR 35 438*a66a82f2SBjorn Andersson #define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 36 439*a66a82f2SBjorn Andersson #define GCC_PCIE_PHY_CFG_AHB_BCR 37 440*a66a82f2SBjorn Andersson #define GCC_PCIE_PHY_COM_BCR 38 441*a66a82f2SBjorn Andersson #define GCC_PCIE_RSCC_BCR 39 442*a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_HS0_MP_BCR 40 443*a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_HS1_MP_BCR 41 444*a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_HS2_MP_BCR 42 445*a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_HS3_MP_BCR 43 446*a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_PRIM_BCR 44 447*a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_SEC_BCR 45 448*a66a82f2SBjorn Andersson #define GCC_SDCC2_BCR 46 449*a66a82f2SBjorn Andersson #define GCC_SDCC4_BCR 47 450*a66a82f2SBjorn Andersson #define GCC_UFS_CARD_BCR 48 451*a66a82f2SBjorn Andersson #define GCC_UFS_PHY_BCR 49 452*a66a82f2SBjorn Andersson #define GCC_USB2_PHY_PRIM_BCR 50 453*a66a82f2SBjorn Andersson #define GCC_USB2_PHY_SEC_BCR 51 454*a66a82f2SBjorn Andersson #define GCC_USB30_MP_BCR 52 455*a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_BCR 53 456*a66a82f2SBjorn Andersson #define GCC_USB30_SEC_BCR 54 457*a66a82f2SBjorn Andersson #define GCC_USB3_DP_PHY_PRIM_BCR 55 458*a66a82f2SBjorn Andersson #define GCC_USB3_DP_PHY_SEC_BCR 56 459*a66a82f2SBjorn Andersson #define GCC_USB3_PHY_PRIM_BCR 57 460*a66a82f2SBjorn Andersson #define GCC_USB3_PHY_SEC_BCR 58 461*a66a82f2SBjorn Andersson #define GCC_USB3_UNIPHY_MP0_BCR 59 462*a66a82f2SBjorn Andersson #define GCC_USB3_UNIPHY_MP1_BCR 60 463*a66a82f2SBjorn Andersson #define GCC_USB3PHY_PHY_PRIM_BCR 61 464*a66a82f2SBjorn Andersson #define GCC_USB3PHY_PHY_SEC_BCR 62 465*a66a82f2SBjorn Andersson #define GCC_USB3UNIPHY_PHY_MP0_BCR 63 466*a66a82f2SBjorn Andersson #define GCC_USB3UNIPHY_PHY_MP1_BCR 64 467*a66a82f2SBjorn Andersson #define GCC_USB4_1_BCR 65 468*a66a82f2SBjorn Andersson #define GCC_USB4_1_DP_PHY_PRIM_BCR 66 469*a66a82f2SBjorn Andersson #define GCC_USB4_1_DPPHY_AUX_BCR 67 470*a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PRIM_BCR 68 471*a66a82f2SBjorn Andersson #define GCC_USB4_BCR 69 472*a66a82f2SBjorn Andersson #define GCC_USB4_DP_PHY_PRIM_BCR 70 473*a66a82f2SBjorn Andersson #define GCC_USB4_DPPHY_AUX_BCR 71 474*a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PRIM_BCR 72 475*a66a82f2SBjorn Andersson #define GCC_USB4PHY_1_PHY_PRIM_BCR 73 476*a66a82f2SBjorn Andersson #define GCC_USB4PHY_PHY_PRIM_BCR 74 477*a66a82f2SBjorn Andersson #define GCC_USB_PHY_CFG_AHB2PHY_BCR 75 478*a66a82f2SBjorn Andersson #define GCC_VIDEO_BCR 76 479*a66a82f2SBjorn Andersson #define GCC_VIDEO_AXI0_CLK_ARES 77 480*a66a82f2SBjorn Andersson #define GCC_VIDEO_AXI1_CLK_ARES 78 481*a66a82f2SBjorn Andersson 482*a66a82f2SBjorn Andersson /* GCC GDSCs */ 483*a66a82f2SBjorn Andersson #define PCIE_0_TUNNEL_GDSC 0 484*a66a82f2SBjorn Andersson #define PCIE_1_TUNNEL_GDSC 1 485*a66a82f2SBjorn Andersson #define PCIE_2A_GDSC 2 486*a66a82f2SBjorn Andersson #define PCIE_2B_GDSC 3 487*a66a82f2SBjorn Andersson #define PCIE_3A_GDSC 4 488*a66a82f2SBjorn Andersson #define PCIE_3B_GDSC 5 489*a66a82f2SBjorn Andersson #define PCIE_4_GDSC 6 490*a66a82f2SBjorn Andersson #define UFS_CARD_GDSC 7 491*a66a82f2SBjorn Andersson #define UFS_PHY_GDSC 8 492*a66a82f2SBjorn Andersson #define USB30_MP_GDSC 9 493*a66a82f2SBjorn Andersson #define USB30_PRIM_GDSC 10 494*a66a82f2SBjorn Andersson #define USB30_SEC_GDSC 11 495*a66a82f2SBjorn Andersson 496*a66a82f2SBjorn Andersson #endif 497