1a66a82f2SBjorn Andersson /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2a66a82f2SBjorn Andersson /* 3a66a82f2SBjorn Andersson * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4a66a82f2SBjorn Andersson * Copyright (c) 2022, Linaro Ltd. 5a66a82f2SBjorn Andersson */ 6a66a82f2SBjorn Andersson 7a66a82f2SBjorn Andersson #ifndef _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H 8a66a82f2SBjorn Andersson #define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H 9a66a82f2SBjorn Andersson 10a66a82f2SBjorn Andersson /* GCC clocks */ 11a66a82f2SBjorn Andersson #define GCC_GPLL0 0 12a66a82f2SBjorn Andersson #define GCC_GPLL0_OUT_EVEN 1 13a66a82f2SBjorn Andersson #define GCC_GPLL2 2 14a66a82f2SBjorn Andersson #define GCC_GPLL4 3 15a66a82f2SBjorn Andersson #define GCC_GPLL7 4 16a66a82f2SBjorn Andersson #define GCC_GPLL8 5 17a66a82f2SBjorn Andersson #define GCC_GPLL9 6 18a66a82f2SBjorn Andersson #define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7 19a66a82f2SBjorn Andersson #define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK 8 20a66a82f2SBjorn Andersson #define GCC_AGGRE_NOC_PCIE_4_AXI_CLK 9 21a66a82f2SBjorn Andersson #define GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK 10 22a66a82f2SBjorn Andersson #define GCC_AGGRE_UFS_CARD_AXI_CLK 11 23a66a82f2SBjorn Andersson #define GCC_AGGRE_UFS_PHY_AXI_CLK 12 24a66a82f2SBjorn Andersson #define GCC_AGGRE_USB3_MP_AXI_CLK 13 25a66a82f2SBjorn Andersson #define GCC_AGGRE_USB3_PRIM_AXI_CLK 14 26a66a82f2SBjorn Andersson #define GCC_AGGRE_USB3_SEC_AXI_CLK 15 27a66a82f2SBjorn Andersson #define GCC_AGGRE_USB4_1_AXI_CLK 16 28a66a82f2SBjorn Andersson #define GCC_AGGRE_USB4_AXI_CLK 17 29a66a82f2SBjorn Andersson #define GCC_AGGRE_USB_NOC_AXI_CLK 18 30a66a82f2SBjorn Andersson #define GCC_AGGRE_USB_NOC_NORTH_AXI_CLK 19 31a66a82f2SBjorn Andersson #define GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK 20 32a66a82f2SBjorn Andersson #define GCC_AHB2PHY0_CLK 21 33a66a82f2SBjorn Andersson #define GCC_AHB2PHY2_CLK 22 34a66a82f2SBjorn Andersson #define GCC_BOOT_ROM_AHB_CLK 23 35a66a82f2SBjorn Andersson #define GCC_CAMERA_AHB_CLK 24 36a66a82f2SBjorn Andersson #define GCC_CAMERA_HF_AXI_CLK 25 37a66a82f2SBjorn Andersson #define GCC_CAMERA_SF_AXI_CLK 26 38a66a82f2SBjorn Andersson #define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 27 39a66a82f2SBjorn Andersson #define GCC_CAMERA_THROTTLE_RT_AXI_CLK 28 40a66a82f2SBjorn Andersson #define GCC_CAMERA_THROTTLE_XO_CLK 29 41a66a82f2SBjorn Andersson #define GCC_CAMERA_XO_CLK 30 42a66a82f2SBjorn Andersson #define GCC_CFG_NOC_USB3_MP_AXI_CLK 31 43a66a82f2SBjorn Andersson #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 32 44a66a82f2SBjorn Andersson #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 33 45a66a82f2SBjorn Andersson #define GCC_CNOC_PCIE0_TUNNEL_CLK 34 46a66a82f2SBjorn Andersson #define GCC_CNOC_PCIE1_TUNNEL_CLK 35 47a66a82f2SBjorn Andersson #define GCC_CNOC_PCIE4_QX_CLK 36 48a66a82f2SBjorn Andersson #define GCC_DDRSS_GPU_AXI_CLK 37 49a66a82f2SBjorn Andersson #define GCC_DDRSS_PCIE_SF_TBU_CLK 38 50a66a82f2SBjorn Andersson #define GCC_DISP1_AHB_CLK 39 51a66a82f2SBjorn Andersson #define GCC_DISP1_HF_AXI_CLK 40 52a66a82f2SBjorn Andersson #define GCC_DISP1_SF_AXI_CLK 41 53a66a82f2SBjorn Andersson #define GCC_DISP1_THROTTLE_NRT_AXI_CLK 42 54a66a82f2SBjorn Andersson #define GCC_DISP1_THROTTLE_RT_AXI_CLK 43 55a66a82f2SBjorn Andersson #define GCC_DISP1_XO_CLK 44 56a66a82f2SBjorn Andersson #define GCC_DISP_AHB_CLK 45 57a66a82f2SBjorn Andersson #define GCC_DISP_HF_AXI_CLK 46 58a66a82f2SBjorn Andersson #define GCC_DISP_SF_AXI_CLK 47 59a66a82f2SBjorn Andersson #define GCC_DISP_THROTTLE_NRT_AXI_CLK 48 60a66a82f2SBjorn Andersson #define GCC_DISP_THROTTLE_RT_AXI_CLK 49 61a66a82f2SBjorn Andersson #define GCC_DISP_XO_CLK 50 62a66a82f2SBjorn Andersson #define GCC_EMAC0_AXI_CLK 51 63a66a82f2SBjorn Andersson #define GCC_EMAC0_PTP_CLK 52 64a66a82f2SBjorn Andersson #define GCC_EMAC0_PTP_CLK_SRC 53 65a66a82f2SBjorn Andersson #define GCC_EMAC0_RGMII_CLK 54 66a66a82f2SBjorn Andersson #define GCC_EMAC0_RGMII_CLK_SRC 55 67a66a82f2SBjorn Andersson #define GCC_EMAC0_SLV_AHB_CLK 56 68a66a82f2SBjorn Andersson #define GCC_EMAC1_AXI_CLK 57 69a66a82f2SBjorn Andersson #define GCC_EMAC1_PTP_CLK 58 70a66a82f2SBjorn Andersson #define GCC_EMAC1_PTP_CLK_SRC 59 71a66a82f2SBjorn Andersson #define GCC_EMAC1_RGMII_CLK 60 72a66a82f2SBjorn Andersson #define GCC_EMAC1_RGMII_CLK_SRC 61 73a66a82f2SBjorn Andersson #define GCC_EMAC1_SLV_AHB_CLK 62 74a66a82f2SBjorn Andersson #define GCC_GP1_CLK 63 75a66a82f2SBjorn Andersson #define GCC_GP1_CLK_SRC 64 76a66a82f2SBjorn Andersson #define GCC_GP2_CLK 65 77a66a82f2SBjorn Andersson #define GCC_GP2_CLK_SRC 66 78a66a82f2SBjorn Andersson #define GCC_GP3_CLK 67 79a66a82f2SBjorn Andersson #define GCC_GP3_CLK_SRC 68 80a66a82f2SBjorn Andersson #define GCC_GP4_CLK 69 81a66a82f2SBjorn Andersson #define GCC_GP4_CLK_SRC 70 82a66a82f2SBjorn Andersson #define GCC_GP5_CLK 71 83a66a82f2SBjorn Andersson #define GCC_GP5_CLK_SRC 72 84a66a82f2SBjorn Andersson #define GCC_GPU_CFG_AHB_CLK 73 85a66a82f2SBjorn Andersson #define GCC_GPU_GPLL0_CLK_SRC 74 86a66a82f2SBjorn Andersson #define GCC_GPU_GPLL0_DIV_CLK_SRC 75 87a66a82f2SBjorn Andersson #define GCC_GPU_IREF_EN 76 88a66a82f2SBjorn Andersson #define GCC_GPU_MEMNOC_GFX_CLK 77 89a66a82f2SBjorn Andersson #define GCC_GPU_SNOC_DVM_GFX_CLK 78 90a66a82f2SBjorn Andersson #define GCC_GPU_TCU_THROTTLE_AHB_CLK 79 91a66a82f2SBjorn Andersson #define GCC_GPU_TCU_THROTTLE_CLK 80 92a66a82f2SBjorn Andersson #define GCC_PCIE0_PHY_RCHNG_CLK 81 93a66a82f2SBjorn Andersson #define GCC_PCIE1_PHY_RCHNG_CLK 82 94a66a82f2SBjorn Andersson #define GCC_PCIE2A_PHY_RCHNG_CLK 83 95a66a82f2SBjorn Andersson #define GCC_PCIE2B_PHY_RCHNG_CLK 84 96a66a82f2SBjorn Andersson #define GCC_PCIE3A_PHY_RCHNG_CLK 85 97a66a82f2SBjorn Andersson #define GCC_PCIE3B_PHY_RCHNG_CLK 86 98a66a82f2SBjorn Andersson #define GCC_PCIE4_PHY_RCHNG_CLK 87 99a66a82f2SBjorn Andersson #define GCC_PCIE_0_AUX_CLK 88 100a66a82f2SBjorn Andersson #define GCC_PCIE_0_AUX_CLK_SRC 89 101a66a82f2SBjorn Andersson #define GCC_PCIE_0_CFG_AHB_CLK 90 102a66a82f2SBjorn Andersson #define GCC_PCIE_0_MSTR_AXI_CLK 91 103a66a82f2SBjorn Andersson #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 92 104a66a82f2SBjorn Andersson #define GCC_PCIE_0_PIPE_CLK 93 105a66a82f2SBjorn Andersson #define GCC_PCIE_0_SLV_AXI_CLK 94 106a66a82f2SBjorn Andersson #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95 107a66a82f2SBjorn Andersson #define GCC_PCIE_1_AUX_CLK 96 108a66a82f2SBjorn Andersson #define GCC_PCIE_1_AUX_CLK_SRC 97 109a66a82f2SBjorn Andersson #define GCC_PCIE_1_CFG_AHB_CLK 98 110a66a82f2SBjorn Andersson #define GCC_PCIE_1_MSTR_AXI_CLK 99 111a66a82f2SBjorn Andersson #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 100 112a66a82f2SBjorn Andersson #define GCC_PCIE_1_PIPE_CLK 101 113a66a82f2SBjorn Andersson #define GCC_PCIE_1_SLV_AXI_CLK 102 114a66a82f2SBjorn Andersson #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 103 115a66a82f2SBjorn Andersson #define GCC_PCIE_2A2B_CLKREF_CLK 104 116a66a82f2SBjorn Andersson #define GCC_PCIE_2A_AUX_CLK 105 117a66a82f2SBjorn Andersson #define GCC_PCIE_2A_AUX_CLK_SRC 106 118a66a82f2SBjorn Andersson #define GCC_PCIE_2A_CFG_AHB_CLK 107 119a66a82f2SBjorn Andersson #define GCC_PCIE_2A_MSTR_AXI_CLK 108 120a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PHY_RCHNG_CLK_SRC 109 121a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PIPE_CLK 110 122a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PIPE_CLK_SRC 111 123a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PIPE_DIV_CLK_SRC 112 124a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PIPEDIV2_CLK 113 125a66a82f2SBjorn Andersson #define GCC_PCIE_2A_SLV_AXI_CLK 114 126a66a82f2SBjorn Andersson #define GCC_PCIE_2A_SLV_Q2A_AXI_CLK 115 127a66a82f2SBjorn Andersson #define GCC_PCIE_2B_AUX_CLK 116 128a66a82f2SBjorn Andersson #define GCC_PCIE_2B_AUX_CLK_SRC 117 129a66a82f2SBjorn Andersson #define GCC_PCIE_2B_CFG_AHB_CLK 118 130a66a82f2SBjorn Andersson #define GCC_PCIE_2B_MSTR_AXI_CLK 119 131a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PHY_RCHNG_CLK_SRC 120 132a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PIPE_CLK 121 133a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PIPE_CLK_SRC 122 134a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PIPE_DIV_CLK_SRC 123 135a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PIPEDIV2_CLK 124 136a66a82f2SBjorn Andersson #define GCC_PCIE_2B_SLV_AXI_CLK 125 137a66a82f2SBjorn Andersson #define GCC_PCIE_2B_SLV_Q2A_AXI_CLK 126 138a66a82f2SBjorn Andersson #define GCC_PCIE_3A3B_CLKREF_CLK 127 139a66a82f2SBjorn Andersson #define GCC_PCIE_3A_AUX_CLK 128 140a66a82f2SBjorn Andersson #define GCC_PCIE_3A_AUX_CLK_SRC 129 141a66a82f2SBjorn Andersson #define GCC_PCIE_3A_CFG_AHB_CLK 130 142a66a82f2SBjorn Andersson #define GCC_PCIE_3A_MSTR_AXI_CLK 131 143a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 132 144a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PIPE_CLK 133 145a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PIPE_CLK_SRC 134 146a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PIPE_DIV_CLK_SRC 135 147a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PIPEDIV2_CLK 136 148a66a82f2SBjorn Andersson #define GCC_PCIE_3A_SLV_AXI_CLK 137 149a66a82f2SBjorn Andersson #define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 138 150a66a82f2SBjorn Andersson #define GCC_PCIE_3B_AUX_CLK 139 151a66a82f2SBjorn Andersson #define GCC_PCIE_3B_AUX_CLK_SRC 140 152a66a82f2SBjorn Andersson #define GCC_PCIE_3B_CFG_AHB_CLK 141 153a66a82f2SBjorn Andersson #define GCC_PCIE_3B_MSTR_AXI_CLK 142 154a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 143 155a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PIPE_CLK 144 156a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PIPE_CLK_SRC 145 157a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 146 158a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PIPEDIV2_CLK 147 159a66a82f2SBjorn Andersson #define GCC_PCIE_3B_SLV_AXI_CLK 148 160a66a82f2SBjorn Andersson #define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 149 161a66a82f2SBjorn Andersson #define GCC_PCIE_4_AUX_CLK 150 162a66a82f2SBjorn Andersson #define GCC_PCIE_4_AUX_CLK_SRC 151 163a66a82f2SBjorn Andersson #define GCC_PCIE_4_CFG_AHB_CLK 152 164a66a82f2SBjorn Andersson #define GCC_PCIE_4_CLKREF_CLK 153 165a66a82f2SBjorn Andersson #define GCC_PCIE_4_MSTR_AXI_CLK 154 166a66a82f2SBjorn Andersson #define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 155 167a66a82f2SBjorn Andersson #define GCC_PCIE_4_PIPE_CLK 156 168a66a82f2SBjorn Andersson #define GCC_PCIE_4_PIPE_CLK_SRC 157 169a66a82f2SBjorn Andersson #define GCC_PCIE_4_PIPE_DIV_CLK_SRC 158 170a66a82f2SBjorn Andersson #define GCC_PCIE_4_PIPEDIV2_CLK 159 171a66a82f2SBjorn Andersson #define GCC_PCIE_4_SLV_AXI_CLK 160 172a66a82f2SBjorn Andersson #define GCC_PCIE_4_SLV_Q2A_AXI_CLK 161 173a66a82f2SBjorn Andersson #define GCC_PCIE_RSCC_AHB_CLK 162 174a66a82f2SBjorn Andersson #define GCC_PCIE_RSCC_XO_CLK 163 175a66a82f2SBjorn Andersson #define GCC_PCIE_RSCC_XO_CLK_SRC 164 176a66a82f2SBjorn Andersson #define GCC_PCIE_THROTTLE_CFG_CLK 165 177a66a82f2SBjorn Andersson #define GCC_PDM2_CLK 166 178a66a82f2SBjorn Andersson #define GCC_PDM2_CLK_SRC 167 179a66a82f2SBjorn Andersson #define GCC_PDM_AHB_CLK 168 180a66a82f2SBjorn Andersson #define GCC_PDM_XO4_CLK 169 181a66a82f2SBjorn Andersson #define GCC_QMIP_CAMERA_NRT_AHB_CLK 170 182a66a82f2SBjorn Andersson #define GCC_QMIP_CAMERA_RT_AHB_CLK 171 183a66a82f2SBjorn Andersson #define GCC_QMIP_DISP1_AHB_CLK 172 184a66a82f2SBjorn Andersson #define GCC_QMIP_DISP1_ROT_AHB_CLK 173 185a66a82f2SBjorn Andersson #define GCC_QMIP_DISP_AHB_CLK 174 186a66a82f2SBjorn Andersson #define GCC_QMIP_DISP_ROT_AHB_CLK 175 187a66a82f2SBjorn Andersson #define GCC_QMIP_VIDEO_CVP_AHB_CLK 176 188a66a82f2SBjorn Andersson #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 177 189a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_CORE_2X_CLK 178 190a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_CORE_CLK 179 191a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_QSPI0_CLK 180 192a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S0_CLK 181 193a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S0_CLK_SRC 182 194a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S1_CLK 183 195a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S1_CLK_SRC 184 196a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S2_CLK 185 197a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S2_CLK_SRC 186 198a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S3_CLK 187 199a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S3_CLK_SRC 188 200a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S4_CLK 189 201a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S4_CLK_SRC 190 202a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC 191 203a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S5_CLK 192 204a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S5_CLK_SRC 193 205a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S6_CLK 194 206a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S6_CLK_SRC 195 207a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S7_CLK 196 208a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP0_S7_CLK_SRC 197 209a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_CORE_2X_CLK 198 210a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_CORE_CLK 199 211a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_QSPI0_CLK 200 212a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S0_CLK 201 213a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S0_CLK_SRC 202 214a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S1_CLK 203 215a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S1_CLK_SRC 204 216a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S2_CLK 205 217a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S2_CLK_SRC 206 218a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S3_CLK 207 219a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S3_CLK_SRC 208 220a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S4_CLK 209 221a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S4_CLK_SRC 210 222a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC 211 223a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S5_CLK 212 224a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S5_CLK_SRC 213 225a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S6_CLK 214 226a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S6_CLK_SRC 215 227a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S7_CLK 216 228a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP1_S7_CLK_SRC 217 229a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_CORE_2X_CLK 218 230a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_CORE_CLK 219 231a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_QSPI0_CLK 220 232a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S0_CLK 221 233a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S0_CLK_SRC 222 234a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S1_CLK 223 235a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S1_CLK_SRC 224 236a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S2_CLK 225 237a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S2_CLK_SRC 226 238a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S3_CLK 227 239a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S3_CLK_SRC 228 240a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S4_CLK 229 241a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S4_CLK_SRC 230 242a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC 231 243a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S5_CLK 232 244a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S5_CLK_SRC 233 245a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S6_CLK 234 246a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S6_CLK_SRC 235 247a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S7_CLK 236 248a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP2_S7_CLK_SRC 237 249a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_0_M_AHB_CLK 238 250a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_0_S_AHB_CLK 239 251a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_1_M_AHB_CLK 240 252a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_1_S_AHB_CLK 241 253a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_2_M_AHB_CLK 242 254a66a82f2SBjorn Andersson #define GCC_QUPV3_WRAP_2_S_AHB_CLK 243 255a66a82f2SBjorn Andersson #define GCC_SDCC2_AHB_CLK 244 256a66a82f2SBjorn Andersson #define GCC_SDCC2_APPS_CLK 245 257a66a82f2SBjorn Andersson #define GCC_SDCC2_APPS_CLK_SRC 246 258a66a82f2SBjorn Andersson #define GCC_SDCC4_AHB_CLK 247 259a66a82f2SBjorn Andersson #define GCC_SDCC4_APPS_CLK 248 260a66a82f2SBjorn Andersson #define GCC_SDCC4_APPS_CLK_SRC 249 261a66a82f2SBjorn Andersson #define GCC_SYS_NOC_USB_AXI_CLK 250 262a66a82f2SBjorn Andersson #define GCC_UFS_1_CARD_CLKREF_CLK 251 263a66a82f2SBjorn Andersson #define GCC_UFS_CARD_AHB_CLK 252 264a66a82f2SBjorn Andersson #define GCC_UFS_CARD_AXI_CLK 253 265a66a82f2SBjorn Andersson #define GCC_UFS_CARD_AXI_CLK_SRC 254 266a66a82f2SBjorn Andersson #define GCC_UFS_CARD_CLKREF_CLK 255 267a66a82f2SBjorn Andersson #define GCC_UFS_CARD_ICE_CORE_CLK 256 268a66a82f2SBjorn Andersson #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 257 269a66a82f2SBjorn Andersson #define GCC_UFS_CARD_PHY_AUX_CLK 258 270a66a82f2SBjorn Andersson #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 259 271a66a82f2SBjorn Andersson #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 260 272a66a82f2SBjorn Andersson #define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 261 273a66a82f2SBjorn Andersson #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 262 274a66a82f2SBjorn Andersson #define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 263 275a66a82f2SBjorn Andersson #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 264 276a66a82f2SBjorn Andersson #define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 265 277a66a82f2SBjorn Andersson #define GCC_UFS_CARD_UNIPRO_CORE_CLK 266 278a66a82f2SBjorn Andersson #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 267 279a66a82f2SBjorn Andersson #define GCC_UFS_PHY_AHB_CLK 268 280a66a82f2SBjorn Andersson #define GCC_UFS_PHY_AXI_CLK 269 281a66a82f2SBjorn Andersson #define GCC_UFS_PHY_AXI_CLK_SRC 270 282a66a82f2SBjorn Andersson #define GCC_UFS_PHY_ICE_CORE_CLK 271 283a66a82f2SBjorn Andersson #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 272 284a66a82f2SBjorn Andersson #define GCC_UFS_PHY_PHY_AUX_CLK 273 285a66a82f2SBjorn Andersson #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 274 286a66a82f2SBjorn Andersson #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 275 287a66a82f2SBjorn Andersson #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 276 288a66a82f2SBjorn Andersson #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 277 289a66a82f2SBjorn Andersson #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 278 290a66a82f2SBjorn Andersson #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 279 291a66a82f2SBjorn Andersson #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 280 292a66a82f2SBjorn Andersson #define GCC_UFS_PHY_UNIPRO_CORE_CLK 281 293a66a82f2SBjorn Andersson #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 282 294a66a82f2SBjorn Andersson #define GCC_UFS_REF_CLKREF_CLK 283 295a66a82f2SBjorn Andersson #define GCC_USB2_HS0_CLKREF_CLK 284 296a66a82f2SBjorn Andersson #define GCC_USB2_HS1_CLKREF_CLK 285 297a66a82f2SBjorn Andersson #define GCC_USB2_HS2_CLKREF_CLK 286 298a66a82f2SBjorn Andersson #define GCC_USB2_HS3_CLKREF_CLK 287 299a66a82f2SBjorn Andersson #define GCC_USB30_MP_MASTER_CLK 288 300a66a82f2SBjorn Andersson #define GCC_USB30_MP_MASTER_CLK_SRC 289 301a66a82f2SBjorn Andersson #define GCC_USB30_MP_MOCK_UTMI_CLK 290 302a66a82f2SBjorn Andersson #define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 291 303a66a82f2SBjorn Andersson #define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 292 304a66a82f2SBjorn Andersson #define GCC_USB30_MP_SLEEP_CLK 293 305a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MASTER_CLK 294 306a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MASTER_CLK_SRC 295 307a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MOCK_UTMI_CLK 296 308a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 297 309a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 298 310a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_SLEEP_CLK 299 311a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MASTER_CLK 300 312a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MASTER_CLK_SRC 301 313a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MOCK_UTMI_CLK 302 314a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 303 315a66a82f2SBjorn Andersson #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 304 316a66a82f2SBjorn Andersson #define GCC_USB30_SEC_SLEEP_CLK 305 317a66a82f2SBjorn Andersson #define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 306 318a66a82f2SBjorn Andersson #define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 307 319a66a82f2SBjorn Andersson #define GCC_USB3_MP0_CLKREF_CLK 308 320a66a82f2SBjorn Andersson #define GCC_USB3_MP1_CLKREF_CLK 309 321a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_AUX_CLK 310 322a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_AUX_CLK_SRC 311 323a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_COM_AUX_CLK 312 324a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_PIPE_0_CLK 313 325a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 314 326a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_PIPE_1_CLK 315 327a66a82f2SBjorn Andersson #define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 316 328a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_AUX_CLK 317 329a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 318 330a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 319 331a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_PIPE_CLK 320 332a66a82f2SBjorn Andersson #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 321 333a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_AUX_CLK 322 334a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 323 335a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_COM_AUX_CLK 324 336a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_PIPE_CLK 325 337a66a82f2SBjorn Andersson #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 326 338a66a82f2SBjorn Andersson #define GCC_USB4_1_CFG_AHB_CLK 327 339a66a82f2SBjorn Andersson #define GCC_USB4_1_DP_CLK 328 340a66a82f2SBjorn Andersson #define GCC_USB4_1_MASTER_CLK 329 341a66a82f2SBjorn Andersson #define GCC_USB4_1_MASTER_CLK_SRC 330 342a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_DP_CLK_SRC 331 343a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 332 344a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 333 345a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PCIE_PIPE_CLK 334 346a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 335 347a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 336 348a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 337 349a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_RX0_CLK 338 350a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_RX0_CLK_SRC 339 351a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_RX1_CLK 340 352a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_RX1_CLK_SRC 341 353a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_SYS_CLK_SRC 342 354a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_USB_PIPE_CLK 343 355a66a82f2SBjorn Andersson #define GCC_USB4_1_SB_IF_CLK 344 356a66a82f2SBjorn Andersson #define GCC_USB4_1_SB_IF_CLK_SRC 345 357a66a82f2SBjorn Andersson #define GCC_USB4_1_SYS_CLK 346 358a66a82f2SBjorn Andersson #define GCC_USB4_1_TMU_CLK 347 359a66a82f2SBjorn Andersson #define GCC_USB4_1_TMU_CLK_SRC 348 360a66a82f2SBjorn Andersson #define GCC_USB4_CFG_AHB_CLK 349 361a66a82f2SBjorn Andersson #define GCC_USB4_CLKREF_CLK 350 362a66a82f2SBjorn Andersson #define GCC_USB4_DP_CLK 351 363a66a82f2SBjorn Andersson #define GCC_USB4_EUD_CLKREF_CLK 352 364a66a82f2SBjorn Andersson #define GCC_USB4_MASTER_CLK 353 365a66a82f2SBjorn Andersson #define GCC_USB4_MASTER_CLK_SRC 354 366a66a82f2SBjorn Andersson #define GCC_USB4_PHY_DP_CLK_SRC 355 367a66a82f2SBjorn Andersson #define GCC_USB4_PHY_P2RR2P_PIPE_CLK 356 368a66a82f2SBjorn Andersson #define GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC 357 369a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PCIE_PIPE_CLK 358 370a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PCIE_PIPE_CLK_SRC 359 371a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC 360 372a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC 361 373a66a82f2SBjorn Andersson #define GCC_USB4_PHY_RX0_CLK 362 374a66a82f2SBjorn Andersson #define GCC_USB4_PHY_RX0_CLK_SRC 363 375a66a82f2SBjorn Andersson #define GCC_USB4_PHY_RX1_CLK 364 376a66a82f2SBjorn Andersson #define GCC_USB4_PHY_RX1_CLK_SRC 365 377a66a82f2SBjorn Andersson #define GCC_USB4_PHY_SYS_CLK_SRC 366 378a66a82f2SBjorn Andersson #define GCC_USB4_PHY_USB_PIPE_CLK 367 379a66a82f2SBjorn Andersson #define GCC_USB4_SB_IF_CLK 368 380a66a82f2SBjorn Andersson #define GCC_USB4_SB_IF_CLK_SRC 369 381a66a82f2SBjorn Andersson #define GCC_USB4_SYS_CLK 370 382a66a82f2SBjorn Andersson #define GCC_USB4_TMU_CLK 371 383a66a82f2SBjorn Andersson #define GCC_USB4_TMU_CLK_SRC 372 384a66a82f2SBjorn Andersson #define GCC_VIDEO_AHB_CLK 373 385a66a82f2SBjorn Andersson #define GCC_VIDEO_AXI0_CLK 374 386a66a82f2SBjorn Andersson #define GCC_VIDEO_AXI1_CLK 375 387a66a82f2SBjorn Andersson #define GCC_VIDEO_CVP_THROTTLE_CLK 376 388a66a82f2SBjorn Andersson #define GCC_VIDEO_VCODEC_THROTTLE_CLK 377 389a66a82f2SBjorn Andersson #define GCC_VIDEO_XO_CLK 378 390a66a82f2SBjorn Andersson #define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 379 391a66a82f2SBjorn Andersson #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 380 392a66a82f2SBjorn Andersson #define GCC_UFS_CARD_AXI_HW_CTL_CLK 381 393a66a82f2SBjorn Andersson #define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 382 394a66a82f2SBjorn Andersson #define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 383 395a66a82f2SBjorn Andersson #define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 384 396a66a82f2SBjorn Andersson #define GCC_UFS_PHY_AXI_HW_CTL_CLK 385 397a66a82f2SBjorn Andersson #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 386 398a66a82f2SBjorn Andersson #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 387 399a66a82f2SBjorn Andersson #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 388 400a66a82f2SBjorn Andersson 401a66a82f2SBjorn Andersson /* GCC resets */ 402a66a82f2SBjorn Andersson #define GCC_EMAC0_BCR 0 403a66a82f2SBjorn Andersson #define GCC_EMAC1_BCR 1 404a66a82f2SBjorn Andersson #define GCC_PCIE_0_LINK_DOWN_BCR 2 405a66a82f2SBjorn Andersson #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3 406a66a82f2SBjorn Andersson #define GCC_PCIE_0_PHY_BCR 4 407a66a82f2SBjorn Andersson #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5 408a66a82f2SBjorn Andersson #define GCC_PCIE_0_TUNNEL_BCR 6 409a66a82f2SBjorn Andersson #define GCC_PCIE_1_LINK_DOWN_BCR 7 410a66a82f2SBjorn Andersson #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8 411a66a82f2SBjorn Andersson #define GCC_PCIE_1_PHY_BCR 9 412a66a82f2SBjorn Andersson #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10 413a66a82f2SBjorn Andersson #define GCC_PCIE_1_TUNNEL_BCR 11 414a66a82f2SBjorn Andersson #define GCC_PCIE_2A_BCR 12 415a66a82f2SBjorn Andersson #define GCC_PCIE_2A_LINK_DOWN_BCR 13 416a66a82f2SBjorn Andersson #define GCC_PCIE_2A_NOCSR_COM_PHY_BCR 14 417a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PHY_BCR 15 418a66a82f2SBjorn Andersson #define GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR 16 419a66a82f2SBjorn Andersson #define GCC_PCIE_2B_BCR 17 420a66a82f2SBjorn Andersson #define GCC_PCIE_2B_LINK_DOWN_BCR 18 421a66a82f2SBjorn Andersson #define GCC_PCIE_2B_NOCSR_COM_PHY_BCR 19 422a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PHY_BCR 20 423a66a82f2SBjorn Andersson #define GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR 21 424a66a82f2SBjorn Andersson #define GCC_PCIE_3A_BCR 22 425a66a82f2SBjorn Andersson #define GCC_PCIE_3A_LINK_DOWN_BCR 23 426a66a82f2SBjorn Andersson #define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 24 427a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PHY_BCR 25 428a66a82f2SBjorn Andersson #define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 26 429a66a82f2SBjorn Andersson #define GCC_PCIE_3B_BCR 27 430a66a82f2SBjorn Andersson #define GCC_PCIE_3B_LINK_DOWN_BCR 28 431a66a82f2SBjorn Andersson #define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 29 432a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PHY_BCR 30 433a66a82f2SBjorn Andersson #define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 31 434a66a82f2SBjorn Andersson #define GCC_PCIE_4_BCR 32 435a66a82f2SBjorn Andersson #define GCC_PCIE_4_LINK_DOWN_BCR 33 436a66a82f2SBjorn Andersson #define GCC_PCIE_4_NOCSR_COM_PHY_BCR 34 437a66a82f2SBjorn Andersson #define GCC_PCIE_4_PHY_BCR 35 438a66a82f2SBjorn Andersson #define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 36 439a66a82f2SBjorn Andersson #define GCC_PCIE_PHY_CFG_AHB_BCR 37 440a66a82f2SBjorn Andersson #define GCC_PCIE_PHY_COM_BCR 38 441a66a82f2SBjorn Andersson #define GCC_PCIE_RSCC_BCR 39 442a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_HS0_MP_BCR 40 443a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_HS1_MP_BCR 41 444a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_HS2_MP_BCR 42 445a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_HS3_MP_BCR 43 446a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_PRIM_BCR 44 447a66a82f2SBjorn Andersson #define GCC_QUSB2PHY_SEC_BCR 45 448a66a82f2SBjorn Andersson #define GCC_SDCC2_BCR 46 449a66a82f2SBjorn Andersson #define GCC_SDCC4_BCR 47 450a66a82f2SBjorn Andersson #define GCC_UFS_CARD_BCR 48 451a66a82f2SBjorn Andersson #define GCC_UFS_PHY_BCR 49 452a66a82f2SBjorn Andersson #define GCC_USB2_PHY_PRIM_BCR 50 453a66a82f2SBjorn Andersson #define GCC_USB2_PHY_SEC_BCR 51 454a66a82f2SBjorn Andersson #define GCC_USB30_MP_BCR 52 455a66a82f2SBjorn Andersson #define GCC_USB30_PRIM_BCR 53 456a66a82f2SBjorn Andersson #define GCC_USB30_SEC_BCR 54 457a66a82f2SBjorn Andersson #define GCC_USB3_DP_PHY_PRIM_BCR 55 458a66a82f2SBjorn Andersson #define GCC_USB3_DP_PHY_SEC_BCR 56 459a66a82f2SBjorn Andersson #define GCC_USB3_PHY_PRIM_BCR 57 460a66a82f2SBjorn Andersson #define GCC_USB3_PHY_SEC_BCR 58 461a66a82f2SBjorn Andersson #define GCC_USB3_UNIPHY_MP0_BCR 59 462a66a82f2SBjorn Andersson #define GCC_USB3_UNIPHY_MP1_BCR 60 463a66a82f2SBjorn Andersson #define GCC_USB3PHY_PHY_PRIM_BCR 61 464a66a82f2SBjorn Andersson #define GCC_USB3PHY_PHY_SEC_BCR 62 465a66a82f2SBjorn Andersson #define GCC_USB3UNIPHY_PHY_MP0_BCR 63 466a66a82f2SBjorn Andersson #define GCC_USB3UNIPHY_PHY_MP1_BCR 64 467a66a82f2SBjorn Andersson #define GCC_USB4_1_BCR 65 468a66a82f2SBjorn Andersson #define GCC_USB4_1_DP_PHY_PRIM_BCR 66 469a66a82f2SBjorn Andersson #define GCC_USB4_1_DPPHY_AUX_BCR 67 470a66a82f2SBjorn Andersson #define GCC_USB4_1_PHY_PRIM_BCR 68 471a66a82f2SBjorn Andersson #define GCC_USB4_BCR 69 472a66a82f2SBjorn Andersson #define GCC_USB4_DP_PHY_PRIM_BCR 70 473a66a82f2SBjorn Andersson #define GCC_USB4_DPPHY_AUX_BCR 71 474a66a82f2SBjorn Andersson #define GCC_USB4_PHY_PRIM_BCR 72 475a66a82f2SBjorn Andersson #define GCC_USB4PHY_1_PHY_PRIM_BCR 73 476a66a82f2SBjorn Andersson #define GCC_USB4PHY_PHY_PRIM_BCR 74 477a66a82f2SBjorn Andersson #define GCC_USB_PHY_CFG_AHB2PHY_BCR 75 478a66a82f2SBjorn Andersson #define GCC_VIDEO_BCR 76 479a66a82f2SBjorn Andersson #define GCC_VIDEO_AXI0_CLK_ARES 77 480a66a82f2SBjorn Andersson #define GCC_VIDEO_AXI1_CLK_ARES 78 481a66a82f2SBjorn Andersson 482a66a82f2SBjorn Andersson /* GCC GDSCs */ 483a66a82f2SBjorn Andersson #define PCIE_0_TUNNEL_GDSC 0 484a66a82f2SBjorn Andersson #define PCIE_1_TUNNEL_GDSC 1 485a66a82f2SBjorn Andersson #define PCIE_2A_GDSC 2 486a66a82f2SBjorn Andersson #define PCIE_2B_GDSC 3 487a66a82f2SBjorn Andersson #define PCIE_3A_GDSC 4 488a66a82f2SBjorn Andersson #define PCIE_3B_GDSC 5 489a66a82f2SBjorn Andersson #define PCIE_4_GDSC 6 490a66a82f2SBjorn Andersson #define UFS_CARD_GDSC 7 491a66a82f2SBjorn Andersson #define UFS_PHY_GDSC 8 492a66a82f2SBjorn Andersson #define USB30_MP_GDSC 9 493a66a82f2SBjorn Andersson #define USB30_PRIM_GDSC 10 494a66a82f2SBjorn Andersson #define USB30_SEC_GDSC 11 49532c2f2a4SAndrew Halaney #define EMAC_0_GDSC 12 49632c2f2a4SAndrew Halaney #define EMAC_1_GDSC 13 497*9eba4db0SKonrad Dybcio #define USB4_1_GDSC 14 498*9eba4db0SKonrad Dybcio #define USB4_GDSC 15 499*9eba4db0SKonrad Dybcio #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 16 500*9eba4db0SKonrad Dybcio #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 17 501*9eba4db0SKonrad Dybcio #define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 18 502*9eba4db0SKonrad Dybcio #define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 19 503*9eba4db0SKonrad Dybcio #define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 20 504*9eba4db0SKonrad Dybcio #define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 21 505*9eba4db0SKonrad Dybcio #define HLOS1_VOTE_TURING_MMU_TBU2_GDSC 22 506*9eba4db0SKonrad Dybcio #define HLOS1_VOTE_TURING_MMU_TBU3_GDSC 23 507a66a82f2SBjorn Andersson 508a66a82f2SBjorn Andersson #endif 509