1b1e010c0SStephen Boyd /* 2b1e010c0SStephen Boyd * Copyright (c) 2015, The Linux Foundation. All rights reserved. 3b1e010c0SStephen Boyd * 4b1e010c0SStephen Boyd * This software is licensed under the terms of the GNU General Public 5b1e010c0SStephen Boyd * License version 2, as published by the Free Software Foundation, and 6b1e010c0SStephen Boyd * may be copied, distributed, and modified under those terms. 7b1e010c0SStephen Boyd * 8b1e010c0SStephen Boyd * This program is distributed in the hope that it will be useful, 9b1e010c0SStephen Boyd * but WITHOUT ANY WARRANTY; without even the implied warranty of 10b1e010c0SStephen Boyd * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11b1e010c0SStephen Boyd * GNU General Public License for more details. 12b1e010c0SStephen Boyd */ 13b1e010c0SStephen Boyd 14b1e010c0SStephen Boyd #ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H 15b1e010c0SStephen Boyd #define _DT_BINDINGS_CLK_MSM_GCC_8996_H 16b1e010c0SStephen Boyd 17b1e010c0SStephen Boyd #define GPLL0_EARLY 0 18b1e010c0SStephen Boyd #define GPLL0 1 19b1e010c0SStephen Boyd #define GPLL1_EARLY 2 20b1e010c0SStephen Boyd #define GPLL1 3 21b1e010c0SStephen Boyd #define GPLL2_EARLY 4 22b1e010c0SStephen Boyd #define GPLL2 5 23b1e010c0SStephen Boyd #define GPLL3_EARLY 6 24b1e010c0SStephen Boyd #define GPLL3 7 25b1e010c0SStephen Boyd #define GPLL4_EARLY 8 26b1e010c0SStephen Boyd #define GPLL4 9 27b1e010c0SStephen Boyd #define SYSTEM_NOC_CLK_SRC 10 28b1e010c0SStephen Boyd #define CONFIG_NOC_CLK_SRC 11 29b1e010c0SStephen Boyd #define PERIPH_NOC_CLK_SRC 12 30b1e010c0SStephen Boyd #define MMSS_BIMC_GFX_CLK_SRC 13 31b1e010c0SStephen Boyd #define USB30_MASTER_CLK_SRC 14 32b1e010c0SStephen Boyd #define USB30_MOCK_UTMI_CLK_SRC 15 33b1e010c0SStephen Boyd #define USB3_PHY_AUX_CLK_SRC 16 34b1e010c0SStephen Boyd #define USB20_MASTER_CLK_SRC 17 35b1e010c0SStephen Boyd #define USB20_MOCK_UTMI_CLK_SRC 18 36b1e010c0SStephen Boyd #define SDCC1_APPS_CLK_SRC 19 37b1e010c0SStephen Boyd #define SDCC1_ICE_CORE_CLK_SRC 20 38b1e010c0SStephen Boyd #define SDCC2_APPS_CLK_SRC 21 39b1e010c0SStephen Boyd #define SDCC3_APPS_CLK_SRC 22 40b1e010c0SStephen Boyd #define SDCC4_APPS_CLK_SRC 23 41b1e010c0SStephen Boyd #define BLSP1_QUP1_SPI_APPS_CLK_SRC 24 42b1e010c0SStephen Boyd #define BLSP1_QUP1_I2C_APPS_CLK_SRC 25 43b1e010c0SStephen Boyd #define BLSP1_UART1_APPS_CLK_SRC 26 44b1e010c0SStephen Boyd #define BLSP1_QUP2_SPI_APPS_CLK_SRC 27 45b1e010c0SStephen Boyd #define BLSP1_QUP2_I2C_APPS_CLK_SRC 28 46b1e010c0SStephen Boyd #define BLSP1_UART2_APPS_CLK_SRC 29 47b1e010c0SStephen Boyd #define BLSP1_QUP3_SPI_APPS_CLK_SRC 30 48b1e010c0SStephen Boyd #define BLSP1_QUP3_I2C_APPS_CLK_SRC 31 49b1e010c0SStephen Boyd #define BLSP1_UART3_APPS_CLK_SRC 32 50b1e010c0SStephen Boyd #define BLSP1_QUP4_SPI_APPS_CLK_SRC 33 51b1e010c0SStephen Boyd #define BLSP1_QUP4_I2C_APPS_CLK_SRC 34 52b1e010c0SStephen Boyd #define BLSP1_UART4_APPS_CLK_SRC 35 53b1e010c0SStephen Boyd #define BLSP1_QUP5_SPI_APPS_CLK_SRC 36 54b1e010c0SStephen Boyd #define BLSP1_QUP5_I2C_APPS_CLK_SRC 37 55b1e010c0SStephen Boyd #define BLSP1_UART5_APPS_CLK_SRC 38 56b1e010c0SStephen Boyd #define BLSP1_QUP6_SPI_APPS_CLK_SRC 39 57b1e010c0SStephen Boyd #define BLSP1_QUP6_I2C_APPS_CLK_SRC 40 58b1e010c0SStephen Boyd #define BLSP1_UART6_APPS_CLK_SRC 41 59b1e010c0SStephen Boyd #define BLSP2_QUP1_SPI_APPS_CLK_SRC 42 60b1e010c0SStephen Boyd #define BLSP2_QUP1_I2C_APPS_CLK_SRC 43 61b1e010c0SStephen Boyd #define BLSP2_UART1_APPS_CLK_SRC 44 62b1e010c0SStephen Boyd #define BLSP2_QUP2_SPI_APPS_CLK_SRC 45 63b1e010c0SStephen Boyd #define BLSP2_QUP2_I2C_APPS_CLK_SRC 46 64b1e010c0SStephen Boyd #define BLSP2_UART2_APPS_CLK_SRC 47 65b1e010c0SStephen Boyd #define BLSP2_QUP3_SPI_APPS_CLK_SRC 48 66b1e010c0SStephen Boyd #define BLSP2_QUP3_I2C_APPS_CLK_SRC 49 67b1e010c0SStephen Boyd #define BLSP2_UART3_APPS_CLK_SRC 50 68b1e010c0SStephen Boyd #define BLSP2_QUP4_SPI_APPS_CLK_SRC 51 69b1e010c0SStephen Boyd #define BLSP2_QUP4_I2C_APPS_CLK_SRC 52 70b1e010c0SStephen Boyd #define BLSP2_UART4_APPS_CLK_SRC 53 71b1e010c0SStephen Boyd #define BLSP2_QUP5_SPI_APPS_CLK_SRC 54 72b1e010c0SStephen Boyd #define BLSP2_QUP5_I2C_APPS_CLK_SRC 55 73b1e010c0SStephen Boyd #define BLSP2_UART5_APPS_CLK_SRC 56 74b1e010c0SStephen Boyd #define BLSP2_QUP6_SPI_APPS_CLK_SRC 57 75b1e010c0SStephen Boyd #define BLSP2_QUP6_I2C_APPS_CLK_SRC 58 76b1e010c0SStephen Boyd #define BLSP2_UART6_APPS_CLK_SRC 59 77b1e010c0SStephen Boyd #define PDM2_CLK_SRC 60 78b1e010c0SStephen Boyd #define TSIF_REF_CLK_SRC 61 79b1e010c0SStephen Boyd #define CE1_CLK_SRC 62 80b1e010c0SStephen Boyd #define GCC_SLEEP_CLK_SRC 63 81b1e010c0SStephen Boyd #define BIMC_CLK_SRC 64 82b1e010c0SStephen Boyd #define HMSS_AHB_CLK_SRC 65 83b1e010c0SStephen Boyd #define BIMC_HMSS_AXI_CLK_SRC 66 84b1e010c0SStephen Boyd #define HMSS_RBCPR_CLK_SRC 67 85b1e010c0SStephen Boyd #define HMSS_GPLL0_CLK_SRC 68 86b1e010c0SStephen Boyd #define GP1_CLK_SRC 69 87b1e010c0SStephen Boyd #define GP2_CLK_SRC 70 88b1e010c0SStephen Boyd #define GP3_CLK_SRC 71 89b1e010c0SStephen Boyd #define PCIE_AUX_CLK_SRC 72 90b1e010c0SStephen Boyd #define UFS_AXI_CLK_SRC 73 91b1e010c0SStephen Boyd #define UFS_ICE_CORE_CLK_SRC 74 92b1e010c0SStephen Boyd #define QSPI_SER_CLK_SRC 75 93b1e010c0SStephen Boyd #define GCC_SYS_NOC_AXI_CLK 76 94b1e010c0SStephen Boyd #define GCC_SYS_NOC_HMSS_AHB_CLK 77 95b1e010c0SStephen Boyd #define GCC_SNOC_CNOC_AHB_CLK 78 96b1e010c0SStephen Boyd #define GCC_SNOC_PNOC_AHB_CLK 79 97b1e010c0SStephen Boyd #define GCC_SYS_NOC_AT_CLK 80 98b1e010c0SStephen Boyd #define GCC_SYS_NOC_USB3_AXI_CLK 81 99b1e010c0SStephen Boyd #define GCC_SYS_NOC_UFS_AXI_CLK 82 100b1e010c0SStephen Boyd #define GCC_CFG_NOC_AHB_CLK 83 101b1e010c0SStephen Boyd #define GCC_PERIPH_NOC_AHB_CLK 84 102b1e010c0SStephen Boyd #define GCC_PERIPH_NOC_USB20_AHB_CLK 85 103b1e010c0SStephen Boyd #define GCC_TIC_CLK 86 104b1e010c0SStephen Boyd #define GCC_IMEM_AXI_CLK 87 105b1e010c0SStephen Boyd #define GCC_MMSS_SYS_NOC_AXI_CLK 88 106b1e010c0SStephen Boyd #define GCC_MMSS_NOC_CFG_AHB_CLK 89 107b1e010c0SStephen Boyd #define GCC_MMSS_BIMC_GFX_CLK 90 108b1e010c0SStephen Boyd #define GCC_USB30_MASTER_CLK 91 109b1e010c0SStephen Boyd #define GCC_USB30_SLEEP_CLK 92 110b1e010c0SStephen Boyd #define GCC_USB30_MOCK_UTMI_CLK 93 111b1e010c0SStephen Boyd #define GCC_USB3_PHY_AUX_CLK 94 112b1e010c0SStephen Boyd #define GCC_USB3_PHY_PIPE_CLK 95 113b1e010c0SStephen Boyd #define GCC_USB20_MASTER_CLK 96 114b1e010c0SStephen Boyd #define GCC_USB20_SLEEP_CLK 97 115b1e010c0SStephen Boyd #define GCC_USB20_MOCK_UTMI_CLK 98 116b1e010c0SStephen Boyd #define GCC_USB_PHY_CFG_AHB2PHY_CLK 99 117b1e010c0SStephen Boyd #define GCC_SDCC1_APPS_CLK 100 118b1e010c0SStephen Boyd #define GCC_SDCC1_AHB_CLK 101 119b1e010c0SStephen Boyd #define GCC_SDCC1_ICE_CORE_CLK 102 120b1e010c0SStephen Boyd #define GCC_SDCC2_APPS_CLK 103 121b1e010c0SStephen Boyd #define GCC_SDCC2_AHB_CLK 104 122b1e010c0SStephen Boyd #define GCC_SDCC3_APPS_CLK 105 123b1e010c0SStephen Boyd #define GCC_SDCC3_AHB_CLK 106 124b1e010c0SStephen Boyd #define GCC_SDCC4_APPS_CLK 107 125b1e010c0SStephen Boyd #define GCC_SDCC4_AHB_CLK 108 126b1e010c0SStephen Boyd #define GCC_BLSP1_AHB_CLK 109 127b1e010c0SStephen Boyd #define GCC_BLSP1_SLEEP_CLK 110 128b1e010c0SStephen Boyd #define GCC_BLSP1_QUP1_SPI_APPS_CLK 111 129b1e010c0SStephen Boyd #define GCC_BLSP1_QUP1_I2C_APPS_CLK 112 130b1e010c0SStephen Boyd #define GCC_BLSP1_UART1_APPS_CLK 113 131b1e010c0SStephen Boyd #define GCC_BLSP1_QUP2_SPI_APPS_CLK 114 132b1e010c0SStephen Boyd #define GCC_BLSP1_QUP2_I2C_APPS_CLK 115 133b1e010c0SStephen Boyd #define GCC_BLSP1_UART2_APPS_CLK 116 134b1e010c0SStephen Boyd #define GCC_BLSP1_QUP3_SPI_APPS_CLK 117 135b1e010c0SStephen Boyd #define GCC_BLSP1_QUP3_I2C_APPS_CLK 118 136b1e010c0SStephen Boyd #define GCC_BLSP1_UART3_APPS_CLK 119 137b1e010c0SStephen Boyd #define GCC_BLSP1_QUP4_SPI_APPS_CLK 120 138b1e010c0SStephen Boyd #define GCC_BLSP1_QUP4_I2C_APPS_CLK 121 139b1e010c0SStephen Boyd #define GCC_BLSP1_UART4_APPS_CLK 122 140b1e010c0SStephen Boyd #define GCC_BLSP1_QUP5_SPI_APPS_CLK 123 141b1e010c0SStephen Boyd #define GCC_BLSP1_QUP5_I2C_APPS_CLK 124 142b1e010c0SStephen Boyd #define GCC_BLSP1_UART5_APPS_CLK 125 143b1e010c0SStephen Boyd #define GCC_BLSP1_QUP6_SPI_APPS_CLK 126 144b1e010c0SStephen Boyd #define GCC_BLSP1_QUP6_I2C_APPS_CLK 127 145b1e010c0SStephen Boyd #define GCC_BLSP1_UART6_APPS_CLK 128 146b1e010c0SStephen Boyd #define GCC_BLSP2_AHB_CLK 129 147b1e010c0SStephen Boyd #define GCC_BLSP2_SLEEP_CLK 130 148b1e010c0SStephen Boyd #define GCC_BLSP2_QUP1_SPI_APPS_CLK 131 149b1e010c0SStephen Boyd #define GCC_BLSP2_QUP1_I2C_APPS_CLK 132 150b1e010c0SStephen Boyd #define GCC_BLSP2_UART1_APPS_CLK 133 151b1e010c0SStephen Boyd #define GCC_BLSP2_QUP2_SPI_APPS_CLK 134 152b1e010c0SStephen Boyd #define GCC_BLSP2_QUP2_I2C_APPS_CLK 135 153b1e010c0SStephen Boyd #define GCC_BLSP2_UART2_APPS_CLK 136 154b1e010c0SStephen Boyd #define GCC_BLSP2_QUP3_SPI_APPS_CLK 137 155b1e010c0SStephen Boyd #define GCC_BLSP2_QUP3_I2C_APPS_CLK 138 156b1e010c0SStephen Boyd #define GCC_BLSP2_UART3_APPS_CLK 139 157b1e010c0SStephen Boyd #define GCC_BLSP2_QUP4_SPI_APPS_CLK 140 158b1e010c0SStephen Boyd #define GCC_BLSP2_QUP4_I2C_APPS_CLK 141 159b1e010c0SStephen Boyd #define GCC_BLSP2_UART4_APPS_CLK 142 160b1e010c0SStephen Boyd #define GCC_BLSP2_QUP5_SPI_APPS_CLK 143 161b1e010c0SStephen Boyd #define GCC_BLSP2_QUP5_I2C_APPS_CLK 144 162b1e010c0SStephen Boyd #define GCC_BLSP2_UART5_APPS_CLK 145 163b1e010c0SStephen Boyd #define GCC_BLSP2_QUP6_SPI_APPS_CLK 146 164b1e010c0SStephen Boyd #define GCC_BLSP2_QUP6_I2C_APPS_CLK 147 165b1e010c0SStephen Boyd #define GCC_BLSP2_UART6_APPS_CLK 148 166b1e010c0SStephen Boyd #define GCC_PDM_AHB_CLK 149 167b1e010c0SStephen Boyd #define GCC_PDM_XO4_CLK 150 168b1e010c0SStephen Boyd #define GCC_PDM2_CLK 151 169b1e010c0SStephen Boyd #define GCC_PRNG_AHB_CLK 152 170b1e010c0SStephen Boyd #define GCC_TSIF_AHB_CLK 153 171b1e010c0SStephen Boyd #define GCC_TSIF_REF_CLK 154 172b1e010c0SStephen Boyd #define GCC_TSIF_INACTIVITY_TIMERS_CLK 155 173b1e010c0SStephen Boyd #define GCC_TCSR_AHB_CLK 156 174b1e010c0SStephen Boyd #define GCC_BOOT_ROM_AHB_CLK 157 175b1e010c0SStephen Boyd #define GCC_MSG_RAM_AHB_CLK 158 176b1e010c0SStephen Boyd #define GCC_TLMM_AHB_CLK 159 177b1e010c0SStephen Boyd #define GCC_TLMM_CLK 160 178b1e010c0SStephen Boyd #define GCC_MPM_AHB_CLK 161 179b1e010c0SStephen Boyd #define GCC_SPMI_SER_CLK 162 180b1e010c0SStephen Boyd #define GCC_SPMI_CNOC_AHB_CLK 163 181b1e010c0SStephen Boyd #define GCC_CE1_CLK 164 182b1e010c0SStephen Boyd #define GCC_CE1_AXI_CLK 165 183b1e010c0SStephen Boyd #define GCC_CE1_AHB_CLK 166 184b1e010c0SStephen Boyd #define GCC_BIMC_HMSS_AXI_CLK 167 185b1e010c0SStephen Boyd #define GCC_BIMC_GFX_CLK 168 186b1e010c0SStephen Boyd #define GCC_HMSS_AHB_CLK 169 187b1e010c0SStephen Boyd #define GCC_HMSS_SLV_AXI_CLK 170 188b1e010c0SStephen Boyd #define GCC_HMSS_MSTR_AXI_CLK 171 189b1e010c0SStephen Boyd #define GCC_HMSS_RBCPR_CLK 172 190b1e010c0SStephen Boyd #define GCC_GP1_CLK 173 191b1e010c0SStephen Boyd #define GCC_GP2_CLK 174 192b1e010c0SStephen Boyd #define GCC_GP3_CLK 175 193b1e010c0SStephen Boyd #define GCC_PCIE_0_SLV_AXI_CLK 176 194b1e010c0SStephen Boyd #define GCC_PCIE_0_MSTR_AXI_CLK 177 195b1e010c0SStephen Boyd #define GCC_PCIE_0_CFG_AHB_CLK 178 196b1e010c0SStephen Boyd #define GCC_PCIE_0_AUX_CLK 179 197b1e010c0SStephen Boyd #define GCC_PCIE_0_PIPE_CLK 180 198b1e010c0SStephen Boyd #define GCC_PCIE_1_SLV_AXI_CLK 181 199b1e010c0SStephen Boyd #define GCC_PCIE_1_MSTR_AXI_CLK 182 200b1e010c0SStephen Boyd #define GCC_PCIE_1_CFG_AHB_CLK 183 201b1e010c0SStephen Boyd #define GCC_PCIE_1_AUX_CLK 184 202b1e010c0SStephen Boyd #define GCC_PCIE_1_PIPE_CLK 185 203b1e010c0SStephen Boyd #define GCC_PCIE_2_SLV_AXI_CLK 186 204b1e010c0SStephen Boyd #define GCC_PCIE_2_MSTR_AXI_CLK 187 205b1e010c0SStephen Boyd #define GCC_PCIE_2_CFG_AHB_CLK 188 206b1e010c0SStephen Boyd #define GCC_PCIE_2_AUX_CLK 189 207b1e010c0SStephen Boyd #define GCC_PCIE_2_PIPE_CLK 190 208b1e010c0SStephen Boyd #define GCC_PCIE_PHY_CFG_AHB_CLK 191 209b1e010c0SStephen Boyd #define GCC_PCIE_PHY_AUX_CLK 192 210b1e010c0SStephen Boyd #define GCC_UFS_AXI_CLK 193 211b1e010c0SStephen Boyd #define GCC_UFS_AHB_CLK 194 212b1e010c0SStephen Boyd #define GCC_UFS_TX_CFG_CLK 195 213b1e010c0SStephen Boyd #define GCC_UFS_RX_CFG_CLK 196 214b1e010c0SStephen Boyd #define GCC_UFS_TX_SYMBOL_0_CLK 197 215b1e010c0SStephen Boyd #define GCC_UFS_RX_SYMBOL_0_CLK 198 216b1e010c0SStephen Boyd #define GCC_UFS_RX_SYMBOL_1_CLK 199 217b1e010c0SStephen Boyd #define GCC_UFS_UNIPRO_CORE_CLK 200 218b1e010c0SStephen Boyd #define GCC_UFS_ICE_CORE_CLK 201 219b1e010c0SStephen Boyd #define GCC_UFS_SYS_CLK_CORE_CLK 202 220b1e010c0SStephen Boyd #define GCC_UFS_TX_SYMBOL_CLK_CORE_CLK 203 221b1e010c0SStephen Boyd #define GCC_AGGRE0_SNOC_AXI_CLK 204 222b1e010c0SStephen Boyd #define GCC_AGGRE0_CNOC_AHB_CLK 205 223b1e010c0SStephen Boyd #define GCC_SMMU_AGGRE0_AXI_CLK 206 224b1e010c0SStephen Boyd #define GCC_SMMU_AGGRE0_AHB_CLK 207 225b1e010c0SStephen Boyd #define GCC_AGGRE1_PNOC_AHB_CLK 208 226b1e010c0SStephen Boyd #define GCC_AGGRE2_UFS_AXI_CLK 209 227b1e010c0SStephen Boyd #define GCC_AGGRE2_USB3_AXI_CLK 210 228b1e010c0SStephen Boyd #define GCC_QSPI_AHB_CLK 211 229b1e010c0SStephen Boyd #define GCC_QSPI_SER_CLK 212 230b1e010c0SStephen Boyd #define GCC_USB3_CLKREF_CLK 213 231b1e010c0SStephen Boyd #define GCC_HDMI_CLKREF_CLK 214 232b1e010c0SStephen Boyd #define GCC_UFS_CLKREF_CLK 215 233b1e010c0SStephen Boyd #define GCC_PCIE_CLKREF_CLK 216 234b1e010c0SStephen Boyd #define GCC_RX2_USB2_CLKREF_CLK 217 235b1e010c0SStephen Boyd #define GCC_RX1_USB2_CLKREF_CLK 218 23669a6beabSSrinivas Kandagatla #define GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK 219 23769a6beabSSrinivas Kandagatla #define GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK 220 238b5677521SRajendra Nayak #define GCC_EDP_CLKREF_CLK 221 239b5677521SRajendra Nayak #define GCC_MSS_CFG_AHB_CLK 222 240b5677521SRajendra Nayak #define GCC_MSS_Q6_BIMC_AXI_CLK 223 241b5677521SRajendra Nayak #define GCC_MSS_SNOC_AXI_CLK 224 242b5677521SRajendra Nayak #define GCC_MSS_MNOC_BIMC_AXI_CLK 225 243b5677521SRajendra Nayak #define GCC_DCC_AHB_CLK 226 244b5677521SRajendra Nayak #define GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK 227 245b5677521SRajendra Nayak #define GCC_MMSS_GPLL0_DIV_CLK 228 246b5677521SRajendra Nayak #define GCC_MSS_GPLL0_DIV_CLK 229 247b1e010c0SStephen Boyd 248b1e010c0SStephen Boyd #define GCC_SYSTEM_NOC_BCR 0 249b1e010c0SStephen Boyd #define GCC_CONFIG_NOC_BCR 1 250b1e010c0SStephen Boyd #define GCC_PERIPH_NOC_BCR 2 251b1e010c0SStephen Boyd #define GCC_IMEM_BCR 3 252b1e010c0SStephen Boyd #define GCC_MMSS_BCR 4 253b1e010c0SStephen Boyd #define GCC_PIMEM_BCR 5 254b1e010c0SStephen Boyd #define GCC_QDSS_BCR 6 255b1e010c0SStephen Boyd #define GCC_USB_30_BCR 7 256b1e010c0SStephen Boyd #define GCC_USB_20_BCR 8 257b1e010c0SStephen Boyd #define GCC_QUSB2PHY_PRIM_BCR 9 258b1e010c0SStephen Boyd #define GCC_QUSB2PHY_SEC_BCR 10 259b1e010c0SStephen Boyd #define GCC_USB_PHY_CFG_AHB2PHY_BCR 11 260b1e010c0SStephen Boyd #define GCC_SDCC1_BCR 12 261b1e010c0SStephen Boyd #define GCC_SDCC2_BCR 13 262b1e010c0SStephen Boyd #define GCC_SDCC3_BCR 14 263b1e010c0SStephen Boyd #define GCC_SDCC4_BCR 15 264b1e010c0SStephen Boyd #define GCC_BLSP1_BCR 16 265b1e010c0SStephen Boyd #define GCC_BLSP1_QUP1_BCR 17 266b1e010c0SStephen Boyd #define GCC_BLSP1_UART1_BCR 18 267b1e010c0SStephen Boyd #define GCC_BLSP1_QUP2_BCR 19 268b1e010c0SStephen Boyd #define GCC_BLSP1_UART2_BCR 20 269b1e010c0SStephen Boyd #define GCC_BLSP1_QUP3_BCR 21 270b1e010c0SStephen Boyd #define GCC_BLSP1_UART3_BCR 22 271b1e010c0SStephen Boyd #define GCC_BLSP1_QUP4_BCR 23 272b1e010c0SStephen Boyd #define GCC_BLSP1_UART4_BCR 24 273b1e010c0SStephen Boyd #define GCC_BLSP1_QUP5_BCR 25 274b1e010c0SStephen Boyd #define GCC_BLSP1_UART5_BCR 26 275b1e010c0SStephen Boyd #define GCC_BLSP1_QUP6_BCR 27 276b1e010c0SStephen Boyd #define GCC_BLSP1_UART6_BCR 28 277b1e010c0SStephen Boyd #define GCC_BLSP2_BCR 29 278b1e010c0SStephen Boyd #define GCC_BLSP2_QUP1_BCR 30 279b1e010c0SStephen Boyd #define GCC_BLSP2_UART1_BCR 31 280b1e010c0SStephen Boyd #define GCC_BLSP2_QUP2_BCR 32 281b1e010c0SStephen Boyd #define GCC_BLSP2_UART2_BCR 33 282b1e010c0SStephen Boyd #define GCC_BLSP2_QUP3_BCR 34 283b1e010c0SStephen Boyd #define GCC_BLSP2_UART3_BCR 35 284b1e010c0SStephen Boyd #define GCC_BLSP2_QUP4_BCR 36 285b1e010c0SStephen Boyd #define GCC_BLSP2_UART4_BCR 37 286b1e010c0SStephen Boyd #define GCC_BLSP2_QUP5_BCR 38 287b1e010c0SStephen Boyd #define GCC_BLSP2_UART5_BCR 39 288b1e010c0SStephen Boyd #define GCC_BLSP2_QUP6_BCR 40 289b1e010c0SStephen Boyd #define GCC_BLSP2_UART6_BCR 41 290b1e010c0SStephen Boyd #define GCC_PDM_BCR 42 291b1e010c0SStephen Boyd #define GCC_PRNG_BCR 43 292b1e010c0SStephen Boyd #define GCC_TSIF_BCR 44 293b1e010c0SStephen Boyd #define GCC_TCSR_BCR 45 294b1e010c0SStephen Boyd #define GCC_BOOT_ROM_BCR 46 295b1e010c0SStephen Boyd #define GCC_MSG_RAM_BCR 47 296b1e010c0SStephen Boyd #define GCC_TLMM_BCR 48 297b1e010c0SStephen Boyd #define GCC_MPM_BCR 49 298b1e010c0SStephen Boyd #define GCC_SEC_CTRL_BCR 50 299b1e010c0SStephen Boyd #define GCC_SPMI_BCR 51 300b1e010c0SStephen Boyd #define GCC_SPDM_BCR 52 301b1e010c0SStephen Boyd #define GCC_CE1_BCR 53 302b1e010c0SStephen Boyd #define GCC_BIMC_BCR 54 303b1e010c0SStephen Boyd #define GCC_SNOC_BUS_TIMEOUT0_BCR 55 304b1e010c0SStephen Boyd #define GCC_SNOC_BUS_TIMEOUT2_BCR 56 305b1e010c0SStephen Boyd #define GCC_SNOC_BUS_TIMEOUT1_BCR 57 306b1e010c0SStephen Boyd #define GCC_SNOC_BUS_TIMEOUT3_BCR 58 307b1e010c0SStephen Boyd #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR 59 308b1e010c0SStephen Boyd #define GCC_PNOC_BUS_TIMEOUT0_BCR 60 309b1e010c0SStephen Boyd #define GCC_PNOC_BUS_TIMEOUT1_BCR 61 310b1e010c0SStephen Boyd #define GCC_PNOC_BUS_TIMEOUT2_BCR 62 311b1e010c0SStephen Boyd #define GCC_PNOC_BUS_TIMEOUT3_BCR 63 312b1e010c0SStephen Boyd #define GCC_PNOC_BUS_TIMEOUT4_BCR 64 313b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT0_BCR 65 314b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT1_BCR 66 315b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT2_BCR 67 316b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT3_BCR 68 317b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT4_BCR 69 318b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT5_BCR 70 319b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT6_BCR 71 320b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT7_BCR 72 321b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT8_BCR 73 322b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT9_BCR 74 323b1e010c0SStephen Boyd #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR 75 324b1e010c0SStephen Boyd #define GCC_APB2JTAG_BCR 76 325b1e010c0SStephen Boyd #define GCC_RBCPR_CX_BCR 77 326b1e010c0SStephen Boyd #define GCC_RBCPR_MX_BCR 78 327b1e010c0SStephen Boyd #define GCC_PCIE_0_BCR 79 328b1e010c0SStephen Boyd #define GCC_PCIE_0_PHY_BCR 80 329b1e010c0SStephen Boyd #define GCC_PCIE_1_BCR 81 330b1e010c0SStephen Boyd #define GCC_PCIE_1_PHY_BCR 82 331b1e010c0SStephen Boyd #define GCC_PCIE_2_BCR 83 332b1e010c0SStephen Boyd #define GCC_PCIE_2_PHY_BCR 84 333b1e010c0SStephen Boyd #define GCC_PCIE_PHY_BCR 85 334b1e010c0SStephen Boyd #define GCC_DCD_BCR 86 335b1e010c0SStephen Boyd #define GCC_OBT_ODT_BCR 87 336b1e010c0SStephen Boyd #define GCC_UFS_BCR 88 337b1e010c0SStephen Boyd #define GCC_SSC_BCR 89 338b1e010c0SStephen Boyd #define GCC_VS_BCR 90 339b1e010c0SStephen Boyd #define GCC_AGGRE0_NOC_BCR 91 340b1e010c0SStephen Boyd #define GCC_AGGRE1_NOC_BCR 92 341b1e010c0SStephen Boyd #define GCC_AGGRE2_NOC_BCR 93 342b1e010c0SStephen Boyd #define GCC_DCC_BCR 94 343b1e010c0SStephen Boyd #define GCC_IPA_BCR 95 344b1e010c0SStephen Boyd #define GCC_QSPI_BCR 96 345b1e010c0SStephen Boyd #define GCC_SKL_BCR 97 346b1e010c0SStephen Boyd #define GCC_MSMPU_BCR 98 347b1e010c0SStephen Boyd #define GCC_MSS_Q6_BCR 99 348b1e010c0SStephen Boyd #define GCC_QREFS_VBG_CAL_BCR 100 34962d15758SSrinivas Kandagatla #define GCC_PCIE_PHY_COM_BCR 101 35062d15758SSrinivas Kandagatla #define GCC_PCIE_PHY_COM_NOCSR_BCR 102 351dc19b6f5SVivek Gautam #define GCC_USB3_PHY_BCR 103 352dc19b6f5SVivek Gautam #define GCC_USB3PHY_PHY_BCR 104 3534263499aSAvaneesh Kumar Dwivedi #define GCC_MSS_RESTART 105 35462d15758SSrinivas Kandagatla 355b1e010c0SStephen Boyd 35652111672SRajendra Nayak /* Indexes for GDSCs */ 35752111672SRajendra Nayak #define AGGRE0_NOC_GDSC 0 35852111672SRajendra Nayak #define HLOS1_VOTE_AGGRE0_NOC_GDSC 1 35952111672SRajendra Nayak #define HLOS1_VOTE_LPASS_ADSP_GDSC 2 36052111672SRajendra Nayak #define HLOS1_VOTE_LPASS_CORE_GDSC 3 36152111672SRajendra Nayak #define USB30_GDSC 4 36252111672SRajendra Nayak #define PCIE0_GDSC 5 36352111672SRajendra Nayak #define PCIE1_GDSC 6 36452111672SRajendra Nayak #define PCIE2_GDSC 7 36552111672SRajendra Nayak #define UFS_GDSC 8 36652111672SRajendra Nayak 367b1e010c0SStephen Boyd #endif 368