1*73d9c10aSBjorn Andersson /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*73d9c10aSBjorn Andersson /* 3*73d9c10aSBjorn Andersson * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4*73d9c10aSBjorn Andersson */ 5*73d9c10aSBjorn Andersson 6*73d9c10aSBjorn Andersson #ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC8280XP_H 7*73d9c10aSBjorn Andersson #define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC8280XP_H 8*73d9c10aSBjorn Andersson 9*73d9c10aSBjorn Andersson /* DISPCC clocks */ 10*73d9c10aSBjorn Andersson #define DISP_CC_PLL0 0 11*73d9c10aSBjorn Andersson #define DISP_CC_PLL1 1 12*73d9c10aSBjorn Andersson #define DISP_CC_PLL1_OUT_EVEN 2 13*73d9c10aSBjorn Andersson #define DISP_CC_PLL2 3 14*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_AHB1_CLK 4 15*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_AHB_CLK 5 16*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_AHB_CLK_SRC 6 17*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_BYTE0_CLK 7 18*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_BYTE0_CLK_SRC 8 19*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 9 20*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_BYTE0_INTF_CLK 10 21*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_BYTE1_CLK 11 22*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_BYTE1_CLK_SRC 12 23*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 13 24*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_BYTE1_INTF_CLK 14 25*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_AUX_CLK 15 26*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 16 27*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_LINK_CLK 17 28*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 18 29*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 19 30*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 20 31*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 21 32*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 22 33*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 23 34*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 24 35*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 25 36*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_AUX_CLK 26 37*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 27 38*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_LINK_CLK 28 39*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 29 40*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 30 41*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 31 42*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 32 43*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 33 44*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 34 45*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 35 46*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 36 47*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_AUX_CLK 37 48*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 38 49*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_LINK_CLK 39 50*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 40 51*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 41 52*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 42 53*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 43 54*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 44 55*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 45 56*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 46 57*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX3_AUX_CLK 47 58*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 48 59*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX3_LINK_CLK 49 60*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 50 61*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 51 62*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 52 63*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 53 64*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 54 65*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_ESC0_CLK 55 66*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_ESC0_CLK_SRC 56 67*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_ESC1_CLK 57 68*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_ESC1_CLK_SRC 58 69*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_MDP1_CLK 59 70*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_MDP_CLK 60 71*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_MDP_CLK_SRC 61 72*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_MDP_LUT1_CLK 62 73*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_MDP_LUT_CLK 63 74*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_NON_GDSC_AHB_CLK 64 75*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_PCLK0_CLK 65 76*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_PCLK0_CLK_SRC 66 77*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_PCLK1_CLK 67 78*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_PCLK1_CLK_SRC 68 79*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_ROT1_CLK 69 80*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_ROT_CLK 70 81*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_ROT_CLK_SRC 71 82*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_RSCC_AHB_CLK 72 83*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_RSCC_VSYNC_CLK 73 84*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_VSYNC1_CLK 74 85*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_VSYNC_CLK 75 86*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_VSYNC_CLK_SRC 76 87*73d9c10aSBjorn Andersson #define DISP_CC_SLEEP_CLK 77 88*73d9c10aSBjorn Andersson #define DISP_CC_SLEEP_CLK_SRC 78 89*73d9c10aSBjorn Andersson #define DISP_CC_XO_CLK 79 90*73d9c10aSBjorn Andersson #define DISP_CC_XO_CLK_SRC 80 91*73d9c10aSBjorn Andersson 92*73d9c10aSBjorn Andersson /* DISPCC resets */ 93*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_CORE_BCR 0 94*73d9c10aSBjorn Andersson #define DISP_CC_MDSS_RSCC_BCR 1 95*73d9c10aSBjorn Andersson 96*73d9c10aSBjorn Andersson /* DISPCC GDSCs */ 97*73d9c10aSBjorn Andersson #define MDSS_GDSC 0 98*73d9c10aSBjorn Andersson #define MDSS_INT2_GDSC 1 99*73d9c10aSBjorn Andersson 100*73d9c10aSBjorn Andersson #endif 101