175a6faf6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21006e3c9SAndrew Bresticker /* 31006e3c9SAndrew Bresticker * Copyright (C) 2014 Google, Inc. 41006e3c9SAndrew Bresticker */ 51006e3c9SAndrew Bresticker 61006e3c9SAndrew Bresticker #ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H 71006e3c9SAndrew Bresticker #define _DT_BINDINGS_CLOCK_PISTACHIO_H 81006e3c9SAndrew Bresticker 91006e3c9SAndrew Bresticker /* PLLs */ 101006e3c9SAndrew Bresticker #define CLK_MIPS_PLL 0 111006e3c9SAndrew Bresticker #define CLK_AUDIO_PLL 1 121006e3c9SAndrew Bresticker #define CLK_RPU_V_PLL 2 131006e3c9SAndrew Bresticker #define CLK_RPU_L_PLL 3 141006e3c9SAndrew Bresticker #define CLK_SYS_PLL 4 151006e3c9SAndrew Bresticker #define CLK_WIFI_PLL 5 161006e3c9SAndrew Bresticker #define CLK_BT_PLL 6 171006e3c9SAndrew Bresticker 181006e3c9SAndrew Bresticker /* Fixed-factor clocks */ 191006e3c9SAndrew Bresticker #define CLK_WIFI_DIV4 16 201006e3c9SAndrew Bresticker #define CLK_WIFI_DIV8 17 211006e3c9SAndrew Bresticker 221006e3c9SAndrew Bresticker /* Gate clocks */ 231006e3c9SAndrew Bresticker #define CLK_MIPS 32 241006e3c9SAndrew Bresticker #define CLK_AUDIO_IN 33 251006e3c9SAndrew Bresticker #define CLK_AUDIO 34 261006e3c9SAndrew Bresticker #define CLK_I2S 35 271006e3c9SAndrew Bresticker #define CLK_SPDIF 36 281006e3c9SAndrew Bresticker #define CLK_AUDIO_DAC 37 291006e3c9SAndrew Bresticker #define CLK_RPU_V 38 301006e3c9SAndrew Bresticker #define CLK_RPU_L 39 311006e3c9SAndrew Bresticker #define CLK_RPU_SLEEP 40 321006e3c9SAndrew Bresticker #define CLK_WIFI_PLL_GATE 41 331006e3c9SAndrew Bresticker #define CLK_RPU_CORE 42 341006e3c9SAndrew Bresticker #define CLK_WIFI_ADC 43 351006e3c9SAndrew Bresticker #define CLK_WIFI_DAC 44 361006e3c9SAndrew Bresticker #define CLK_USB_PHY 45 371006e3c9SAndrew Bresticker #define CLK_ENET_IN 46 381006e3c9SAndrew Bresticker #define CLK_ENET 47 391006e3c9SAndrew Bresticker #define CLK_UART0 48 401006e3c9SAndrew Bresticker #define CLK_UART1 49 411006e3c9SAndrew Bresticker #define CLK_PERIPH_SYS 50 421006e3c9SAndrew Bresticker #define CLK_SPI0 51 431006e3c9SAndrew Bresticker #define CLK_SPI1 52 441006e3c9SAndrew Bresticker #define CLK_EVENT_TIMER 53 451006e3c9SAndrew Bresticker #define CLK_AUX_ADC_INTERNAL 54 461006e3c9SAndrew Bresticker #define CLK_AUX_ADC 55 471006e3c9SAndrew Bresticker #define CLK_SD_HOST 56 481006e3c9SAndrew Bresticker #define CLK_BT 57 491006e3c9SAndrew Bresticker #define CLK_BT_DIV4 58 501006e3c9SAndrew Bresticker #define CLK_BT_DIV8 59 511006e3c9SAndrew Bresticker #define CLK_BT_1MHZ 60 521006e3c9SAndrew Bresticker 531006e3c9SAndrew Bresticker /* Divider clocks */ 541006e3c9SAndrew Bresticker #define CLK_MIPS_INTERNAL_DIV 64 551006e3c9SAndrew Bresticker #define CLK_MIPS_DIV 65 561006e3c9SAndrew Bresticker #define CLK_AUDIO_DIV 66 571006e3c9SAndrew Bresticker #define CLK_I2S_DIV 67 581006e3c9SAndrew Bresticker #define CLK_SPDIF_DIV 68 591006e3c9SAndrew Bresticker #define CLK_AUDIO_DAC_DIV 69 601006e3c9SAndrew Bresticker #define CLK_RPU_V_DIV 70 611006e3c9SAndrew Bresticker #define CLK_RPU_L_DIV 71 621006e3c9SAndrew Bresticker #define CLK_RPU_SLEEP_DIV 72 631006e3c9SAndrew Bresticker #define CLK_RPU_CORE_DIV 73 641006e3c9SAndrew Bresticker #define CLK_USB_PHY_DIV 74 651006e3c9SAndrew Bresticker #define CLK_ENET_DIV 75 661006e3c9SAndrew Bresticker #define CLK_UART0_INTERNAL_DIV 76 671006e3c9SAndrew Bresticker #define CLK_UART0_DIV 77 681006e3c9SAndrew Bresticker #define CLK_UART1_INTERNAL_DIV 78 691006e3c9SAndrew Bresticker #define CLK_UART1_DIV 79 701006e3c9SAndrew Bresticker #define CLK_SYS_INTERNAL_DIV 80 711006e3c9SAndrew Bresticker #define CLK_SPI0_INTERNAL_DIV 81 721006e3c9SAndrew Bresticker #define CLK_SPI0_DIV 82 731006e3c9SAndrew Bresticker #define CLK_SPI1_INTERNAL_DIV 83 741006e3c9SAndrew Bresticker #define CLK_SPI1_DIV 84 751006e3c9SAndrew Bresticker #define CLK_EVENT_TIMER_INTERNAL_DIV 85 761006e3c9SAndrew Bresticker #define CLK_EVENT_TIMER_DIV 86 771006e3c9SAndrew Bresticker #define CLK_AUX_ADC_INTERNAL_DIV 87 781006e3c9SAndrew Bresticker #define CLK_AUX_ADC_DIV 88 791006e3c9SAndrew Bresticker #define CLK_SD_HOST_DIV 89 801006e3c9SAndrew Bresticker #define CLK_BT_DIV 90 811006e3c9SAndrew Bresticker #define CLK_BT_DIV4_DIV 91 821006e3c9SAndrew Bresticker #define CLK_BT_DIV8_DIV 92 831006e3c9SAndrew Bresticker #define CLK_BT_1MHZ_INTERNAL_DIV 93 841006e3c9SAndrew Bresticker #define CLK_BT_1MHZ_DIV 94 851006e3c9SAndrew Bresticker 861006e3c9SAndrew Bresticker /* Mux clocks */ 871006e3c9SAndrew Bresticker #define CLK_AUDIO_REF_MUX 96 881006e3c9SAndrew Bresticker #define CLK_MIPS_PLL_MUX 97 891006e3c9SAndrew Bresticker #define CLK_AUDIO_PLL_MUX 98 901006e3c9SAndrew Bresticker #define CLK_AUDIO_MUX 99 911006e3c9SAndrew Bresticker #define CLK_RPU_V_PLL_MUX 100 921006e3c9SAndrew Bresticker #define CLK_RPU_L_PLL_MUX 101 931006e3c9SAndrew Bresticker #define CLK_RPU_L_MUX 102 941006e3c9SAndrew Bresticker #define CLK_WIFI_PLL_MUX 103 951006e3c9SAndrew Bresticker #define CLK_WIFI_DIV4_MUX 104 961006e3c9SAndrew Bresticker #define CLK_WIFI_DIV8_MUX 105 971006e3c9SAndrew Bresticker #define CLK_RPU_CORE_MUX 106 981006e3c9SAndrew Bresticker #define CLK_SYS_PLL_MUX 107 991006e3c9SAndrew Bresticker #define CLK_ENET_MUX 108 1001006e3c9SAndrew Bresticker #define CLK_EVENT_TIMER_MUX 109 1011006e3c9SAndrew Bresticker #define CLK_SD_HOST_MUX 110 1021006e3c9SAndrew Bresticker #define CLK_BT_PLL_MUX 111 1031006e3c9SAndrew Bresticker #define CLK_DEBUG_MUX 112 1041006e3c9SAndrew Bresticker 1051006e3c9SAndrew Bresticker #define CLK_NR_CLKS 113 1061006e3c9SAndrew Bresticker 1071006e3c9SAndrew Bresticker /* Peripheral gate clocks */ 1081006e3c9SAndrew Bresticker #define PERIPH_CLK_SYS 0 1091006e3c9SAndrew Bresticker #define PERIPH_CLK_SYS_BUS 1 1101006e3c9SAndrew Bresticker #define PERIPH_CLK_DDR 2 1111006e3c9SAndrew Bresticker #define PERIPH_CLK_ROM 3 1121006e3c9SAndrew Bresticker #define PERIPH_CLK_COUNTER_FAST 4 1131006e3c9SAndrew Bresticker #define PERIPH_CLK_COUNTER_SLOW 5 1141006e3c9SAndrew Bresticker #define PERIPH_CLK_IR 6 1151006e3c9SAndrew Bresticker #define PERIPH_CLK_WD 7 1161006e3c9SAndrew Bresticker #define PERIPH_CLK_PDM 8 1171006e3c9SAndrew Bresticker #define PERIPH_CLK_PWM 9 1181006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C0 10 1191006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C1 11 1201006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C2 12 1211006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C3 13 1221006e3c9SAndrew Bresticker 1231006e3c9SAndrew Bresticker /* Peripheral divider clocks */ 1241006e3c9SAndrew Bresticker #define PERIPH_CLK_ROM_DIV 32 1251006e3c9SAndrew Bresticker #define PERIPH_CLK_COUNTER_FAST_DIV 33 1261006e3c9SAndrew Bresticker #define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34 1271006e3c9SAndrew Bresticker #define PERIPH_CLK_COUNTER_SLOW_DIV 35 1281006e3c9SAndrew Bresticker #define PERIPH_CLK_IR_PRE_DIV 36 1291006e3c9SAndrew Bresticker #define PERIPH_CLK_IR_DIV 37 1301006e3c9SAndrew Bresticker #define PERIPH_CLK_WD_PRE_DIV 38 1311006e3c9SAndrew Bresticker #define PERIPH_CLK_WD_DIV 39 1321006e3c9SAndrew Bresticker #define PERIPH_CLK_PDM_PRE_DIV 40 1331006e3c9SAndrew Bresticker #define PERIPH_CLK_PDM_DIV 41 1341006e3c9SAndrew Bresticker #define PERIPH_CLK_PWM_PRE_DIV 42 1351006e3c9SAndrew Bresticker #define PERIPH_CLK_PWM_DIV 43 1361006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C0_PRE_DIV 44 1371006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C0_DIV 45 1381006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C1_PRE_DIV 46 1391006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C1_DIV 47 1401006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C2_PRE_DIV 48 1411006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C2_DIV 49 1421006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C3_PRE_DIV 50 1431006e3c9SAndrew Bresticker #define PERIPH_CLK_I2C3_DIV 51 1441006e3c9SAndrew Bresticker 1451006e3c9SAndrew Bresticker #define PERIPH_CLK_NR_CLKS 52 1461006e3c9SAndrew Bresticker 1471006e3c9SAndrew Bresticker /* System gate clocks */ 1481006e3c9SAndrew Bresticker #define SYS_CLK_I2C0 0 1491006e3c9SAndrew Bresticker #define SYS_CLK_I2C1 1 1501006e3c9SAndrew Bresticker #define SYS_CLK_I2C2 2 1511006e3c9SAndrew Bresticker #define SYS_CLK_I2C3 3 1521006e3c9SAndrew Bresticker #define SYS_CLK_I2S_IN 4 1531006e3c9SAndrew Bresticker #define SYS_CLK_PAUD_OUT 5 1541006e3c9SAndrew Bresticker #define SYS_CLK_SPDIF_OUT 6 1551006e3c9SAndrew Bresticker #define SYS_CLK_SPI0_MASTER 7 1561006e3c9SAndrew Bresticker #define SYS_CLK_SPI0_SLAVE 8 1571006e3c9SAndrew Bresticker #define SYS_CLK_PWM 9 1581006e3c9SAndrew Bresticker #define SYS_CLK_UART0 10 1591006e3c9SAndrew Bresticker #define SYS_CLK_UART1 11 1601006e3c9SAndrew Bresticker #define SYS_CLK_SPI1 12 1611006e3c9SAndrew Bresticker #define SYS_CLK_MDC 13 1621006e3c9SAndrew Bresticker #define SYS_CLK_SD_HOST 14 1631006e3c9SAndrew Bresticker #define SYS_CLK_ENET 15 1641006e3c9SAndrew Bresticker #define SYS_CLK_IR 16 1651006e3c9SAndrew Bresticker #define SYS_CLK_WD 17 1661006e3c9SAndrew Bresticker #define SYS_CLK_TIMER 18 1671006e3c9SAndrew Bresticker #define SYS_CLK_I2S_OUT 24 1681006e3c9SAndrew Bresticker #define SYS_CLK_SPDIF_IN 25 1691006e3c9SAndrew Bresticker #define SYS_CLK_EVENT_TIMER 26 1701006e3c9SAndrew Bresticker #define SYS_CLK_HASH 27 1711006e3c9SAndrew Bresticker 1721006e3c9SAndrew Bresticker #define SYS_CLK_NR_CLKS 28 1731006e3c9SAndrew Bresticker 1741006e3c9SAndrew Bresticker /* Gates for external input clocks */ 1751006e3c9SAndrew Bresticker #define EXT_CLK_AUDIO_IN 0 1761006e3c9SAndrew Bresticker #define EXT_CLK_ENET_IN 1 1771006e3c9SAndrew Bresticker 1781006e3c9SAndrew Bresticker #define EXT_CLK_NR_CLKS 2 1791006e3c9SAndrew Bresticker 1801006e3c9SAndrew Bresticker #endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */ 181