1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2019 MediaTek Inc. 4 * Copyright (c) 2019 BayLibre, SAS. 5 * Author: James Liao <jamesjj.liao@mediatek.com> 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_MT8516_H 9 #define _DT_BINDINGS_CLK_MT8516_H 10 11 /* TOPCKGEN */ 12 13 #define CLK_TOP_CLK_NULL 0 14 #define CLK_TOP_I2S_INFRA_BCK 1 15 #define CLK_TOP_MEMPLL 2 16 #define CLK_TOP_DMPLL 3 17 #define CLK_TOP_MAINPLL_D2 4 18 #define CLK_TOP_MAINPLL_D4 5 19 #define CLK_TOP_MAINPLL_D8 6 20 #define CLK_TOP_MAINPLL_D16 7 21 #define CLK_TOP_MAINPLL_D11 8 22 #define CLK_TOP_MAINPLL_D22 9 23 #define CLK_TOP_MAINPLL_D3 10 24 #define CLK_TOP_MAINPLL_D6 11 25 #define CLK_TOP_MAINPLL_D12 12 26 #define CLK_TOP_MAINPLL_D5 13 27 #define CLK_TOP_MAINPLL_D10 14 28 #define CLK_TOP_MAINPLL_D20 15 29 #define CLK_TOP_MAINPLL_D40 16 30 #define CLK_TOP_MAINPLL_D7 17 31 #define CLK_TOP_MAINPLL_D14 18 32 #define CLK_TOP_UNIVPLL_D2 19 33 #define CLK_TOP_UNIVPLL_D4 20 34 #define CLK_TOP_UNIVPLL_D8 21 35 #define CLK_TOP_UNIVPLL_D16 22 36 #define CLK_TOP_UNIVPLL_D3 23 37 #define CLK_TOP_UNIVPLL_D6 24 38 #define CLK_TOP_UNIVPLL_D12 25 39 #define CLK_TOP_UNIVPLL_D24 26 40 #define CLK_TOP_UNIVPLL_D5 27 41 #define CLK_TOP_UNIVPLL_D20 28 42 #define CLK_TOP_MMPLL380M 29 43 #define CLK_TOP_MMPLL_D2 30 44 #define CLK_TOP_MMPLL_200M 31 45 #define CLK_TOP_USB_PHY48M 32 46 #define CLK_TOP_APLL1 33 47 #define CLK_TOP_APLL1_D2 34 48 #define CLK_TOP_APLL1_D4 35 49 #define CLK_TOP_APLL1_D8 36 50 #define CLK_TOP_APLL2 37 51 #define CLK_TOP_APLL2_D2 38 52 #define CLK_TOP_APLL2_D4 39 53 #define CLK_TOP_APLL2_D8 40 54 #define CLK_TOP_CLK26M 41 55 #define CLK_TOP_CLK26M_D2 42 56 #define CLK_TOP_AHB_INFRA_D2 43 57 #define CLK_TOP_NFI1X 44 58 #define CLK_TOP_ETH_D2 45 59 #define CLK_TOP_THEM 46 60 #define CLK_TOP_APDMA 47 61 #define CLK_TOP_I2C0 48 62 #define CLK_TOP_I2C1 49 63 #define CLK_TOP_AUXADC1 50 64 #define CLK_TOP_NFI 51 65 #define CLK_TOP_NFIECC 52 66 #define CLK_TOP_DEBUGSYS 53 67 #define CLK_TOP_PWM 54 68 #define CLK_TOP_UART0 55 69 #define CLK_TOP_UART1 56 70 #define CLK_TOP_BTIF 57 71 #define CLK_TOP_USB 58 72 #define CLK_TOP_FLASHIF_26M 59 73 #define CLK_TOP_AUXADC2 60 74 #define CLK_TOP_I2C2 61 75 #define CLK_TOP_MSDC0 62 76 #define CLK_TOP_MSDC1 63 77 #define CLK_TOP_NFI2X 64 78 #define CLK_TOP_PMICWRAP_AP 65 79 #define CLK_TOP_SEJ 66 80 #define CLK_TOP_MEMSLP_DLYER 67 81 #define CLK_TOP_SPI 68 82 #define CLK_TOP_APXGPT 69 83 #define CLK_TOP_AUDIO 70 84 #define CLK_TOP_PMICWRAP_MD 71 85 #define CLK_TOP_PMICWRAP_CONN 72 86 #define CLK_TOP_PMICWRAP_26M 73 87 #define CLK_TOP_AUX_ADC 74 88 #define CLK_TOP_AUX_TP 75 89 #define CLK_TOP_MSDC2 76 90 #define CLK_TOP_RBIST 77 91 #define CLK_TOP_NFI_BUS 78 92 #define CLK_TOP_GCE 79 93 #define CLK_TOP_TRNG 80 94 #define CLK_TOP_SEJ_13M 81 95 #define CLK_TOP_AES 82 96 #define CLK_TOP_PWM_B 83 97 #define CLK_TOP_PWM1_FB 84 98 #define CLK_TOP_PWM2_FB 85 99 #define CLK_TOP_PWM3_FB 86 100 #define CLK_TOP_PWM4_FB 87 101 #define CLK_TOP_PWM5_FB 88 102 #define CLK_TOP_USB_1P 89 103 #define CLK_TOP_FLASHIF_FREERUN 90 104 #define CLK_TOP_66M_ETH 91 105 #define CLK_TOP_133M_ETH 92 106 #define CLK_TOP_FETH_25M 93 107 #define CLK_TOP_FETH_50M 94 108 #define CLK_TOP_FLASHIF_AXI 95 109 #define CLK_TOP_USBIF 96 110 #define CLK_TOP_UART2 97 111 #define CLK_TOP_BSI 98 112 #define CLK_TOP_RG_SPINOR 99 113 #define CLK_TOP_RG_MSDC2 100 114 #define CLK_TOP_RG_ETH 101 115 #define CLK_TOP_RG_AUD1 102 116 #define CLK_TOP_RG_AUD2 103 117 #define CLK_TOP_RG_AUD_ENGEN1 104 118 #define CLK_TOP_RG_AUD_ENGEN2 105 119 #define CLK_TOP_RG_I2C 106 120 #define CLK_TOP_RG_PWM_INFRA 107 121 #define CLK_TOP_RG_AUD_SPDIF_IN 108 122 #define CLK_TOP_RG_UART2 109 123 #define CLK_TOP_RG_BSI 110 124 #define CLK_TOP_RG_DBG_ATCLK 111 125 #define CLK_TOP_RG_NFIECC 112 126 #define CLK_TOP_RG_APLL1_D2_EN 113 127 #define CLK_TOP_RG_APLL1_D4_EN 114 128 #define CLK_TOP_RG_APLL1_D8_EN 115 129 #define CLK_TOP_RG_APLL2_D2_EN 116 130 #define CLK_TOP_RG_APLL2_D4_EN 117 131 #define CLK_TOP_RG_APLL2_D8_EN 118 132 #define CLK_TOP_APLL12_DIV0 119 133 #define CLK_TOP_APLL12_DIV1 120 134 #define CLK_TOP_APLL12_DIV2 121 135 #define CLK_TOP_APLL12_DIV3 122 136 #define CLK_TOP_APLL12_DIV4 123 137 #define CLK_TOP_APLL12_DIV4B 124 138 #define CLK_TOP_APLL12_DIV5 125 139 #define CLK_TOP_APLL12_DIV5B 126 140 #define CLK_TOP_APLL12_DIV6 127 141 #define CLK_TOP_UART0_SEL 128 142 #define CLK_TOP_EMI_DDRPHY_SEL 129 143 #define CLK_TOP_AHB_INFRA_SEL 130 144 #define CLK_TOP_MSDC0_SEL 131 145 #define CLK_TOP_UART1_SEL 132 146 #define CLK_TOP_MSDC1_SEL 133 147 #define CLK_TOP_PMICSPI_SEL 134 148 #define CLK_TOP_QAXI_AUD26M_SEL 135 149 #define CLK_TOP_AUD_INTBUS_SEL 136 150 #define CLK_TOP_NFI2X_PAD_SEL 137 151 #define CLK_TOP_NFI1X_PAD_SEL 138 152 #define CLK_TOP_DDRPHYCFG_SEL 139 153 #define CLK_TOP_USB_78M_SEL 140 154 #define CLK_TOP_SPINOR_SEL 141 155 #define CLK_TOP_MSDC2_SEL 142 156 #define CLK_TOP_ETH_SEL 143 157 #define CLK_TOP_AUD1_SEL 144 158 #define CLK_TOP_AUD2_SEL 145 159 #define CLK_TOP_AUD_ENGEN1_SEL 146 160 #define CLK_TOP_AUD_ENGEN2_SEL 147 161 #define CLK_TOP_I2C_SEL 148 162 #define CLK_TOP_AUD_I2S0_M_SEL 149 163 #define CLK_TOP_AUD_I2S1_M_SEL 150 164 #define CLK_TOP_AUD_I2S2_M_SEL 151 165 #define CLK_TOP_AUD_I2S3_M_SEL 152 166 #define CLK_TOP_AUD_I2S4_M_SEL 153 167 #define CLK_TOP_AUD_I2S5_M_SEL 154 168 #define CLK_TOP_AUD_SPDIF_B_SEL 155 169 #define CLK_TOP_PWM_SEL 156 170 #define CLK_TOP_SPI_SEL 157 171 #define CLK_TOP_AUD_SPDIFIN_SEL 158 172 #define CLK_TOP_UART2_SEL 159 173 #define CLK_TOP_BSI_SEL 160 174 #define CLK_TOP_DBG_ATCLK_SEL 161 175 #define CLK_TOP_CSW_NFIECC_SEL 162 176 #define CLK_TOP_NFIECC_SEL 163 177 #define CLK_TOP_APLL12_CK_DIV0 164 178 #define CLK_TOP_APLL12_CK_DIV1 165 179 #define CLK_TOP_APLL12_CK_DIV2 166 180 #define CLK_TOP_APLL12_CK_DIV3 167 181 #define CLK_TOP_APLL12_CK_DIV4 168 182 #define CLK_TOP_APLL12_CK_DIV4B 169 183 #define CLK_TOP_APLL12_CK_DIV5 170 184 #define CLK_TOP_APLL12_CK_DIV5B 171 185 #define CLK_TOP_APLL12_CK_DIV6 172 186 #define CLK_TOP_USB_78M 173 187 #define CLK_TOP_MSDC0_INFRA 174 188 #define CLK_TOP_MSDC1_INFRA 175 189 #define CLK_TOP_MSDC2_INFRA 176 190 #define CLK_TOP_NR_CLK 177 191 192 #endif /* _DT_BINDINGS_CLK_MT8516_H */ 193