167ea1516SFabien Parent /* SPDX-License-Identifier: GPL-2.0 */ 267ea1516SFabien Parent /* 367ea1516SFabien Parent * Copyright (c) 2019 MediaTek Inc. 467ea1516SFabien Parent * Copyright (c) 2019 BayLibre, SAS. 567ea1516SFabien Parent * Author: James Liao <jamesjj.liao@mediatek.com> 667ea1516SFabien Parent */ 767ea1516SFabien Parent 867ea1516SFabien Parent #ifndef _DT_BINDINGS_CLK_MT8516_H 967ea1516SFabien Parent #define _DT_BINDINGS_CLK_MT8516_H 1067ea1516SFabien Parent 1167ea1516SFabien Parent /* TOPCKGEN */ 1267ea1516SFabien Parent 1367ea1516SFabien Parent #define CLK_TOP_CLK_NULL 0 1467ea1516SFabien Parent #define CLK_TOP_I2S_INFRA_BCK 1 1567ea1516SFabien Parent #define CLK_TOP_MEMPLL 2 1667ea1516SFabien Parent #define CLK_TOP_DMPLL 3 1767ea1516SFabien Parent #define CLK_TOP_MAINPLL_D2 4 1867ea1516SFabien Parent #define CLK_TOP_MAINPLL_D4 5 1967ea1516SFabien Parent #define CLK_TOP_MAINPLL_D8 6 2067ea1516SFabien Parent #define CLK_TOP_MAINPLL_D16 7 2167ea1516SFabien Parent #define CLK_TOP_MAINPLL_D11 8 2267ea1516SFabien Parent #define CLK_TOP_MAINPLL_D22 9 2367ea1516SFabien Parent #define CLK_TOP_MAINPLL_D3 10 2467ea1516SFabien Parent #define CLK_TOP_MAINPLL_D6 11 2567ea1516SFabien Parent #define CLK_TOP_MAINPLL_D12 12 2667ea1516SFabien Parent #define CLK_TOP_MAINPLL_D5 13 2767ea1516SFabien Parent #define CLK_TOP_MAINPLL_D10 14 2867ea1516SFabien Parent #define CLK_TOP_MAINPLL_D20 15 2967ea1516SFabien Parent #define CLK_TOP_MAINPLL_D40 16 3067ea1516SFabien Parent #define CLK_TOP_MAINPLL_D7 17 3167ea1516SFabien Parent #define CLK_TOP_MAINPLL_D14 18 3267ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D2 19 3367ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D4 20 3467ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D8 21 3567ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D16 22 3667ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D3 23 3767ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D6 24 3867ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D12 25 3967ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D24 26 4067ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D5 27 4167ea1516SFabien Parent #define CLK_TOP_UNIVPLL_D20 28 4267ea1516SFabien Parent #define CLK_TOP_MMPLL380M 29 4367ea1516SFabien Parent #define CLK_TOP_MMPLL_D2 30 4467ea1516SFabien Parent #define CLK_TOP_MMPLL_200M 31 4567ea1516SFabien Parent #define CLK_TOP_USB_PHY48M 32 4667ea1516SFabien Parent #define CLK_TOP_APLL1 33 4767ea1516SFabien Parent #define CLK_TOP_APLL1_D2 34 4867ea1516SFabien Parent #define CLK_TOP_APLL1_D4 35 4967ea1516SFabien Parent #define CLK_TOP_APLL1_D8 36 5067ea1516SFabien Parent #define CLK_TOP_APLL2 37 5167ea1516SFabien Parent #define CLK_TOP_APLL2_D2 38 5267ea1516SFabien Parent #define CLK_TOP_APLL2_D4 39 5367ea1516SFabien Parent #define CLK_TOP_APLL2_D8 40 5467ea1516SFabien Parent #define CLK_TOP_CLK26M 41 5567ea1516SFabien Parent #define CLK_TOP_CLK26M_D2 42 5667ea1516SFabien Parent #define CLK_TOP_AHB_INFRA_D2 43 5767ea1516SFabien Parent #define CLK_TOP_NFI1X 44 5867ea1516SFabien Parent #define CLK_TOP_ETH_D2 45 5967ea1516SFabien Parent #define CLK_TOP_THEM 46 6067ea1516SFabien Parent #define CLK_TOP_APDMA 47 6167ea1516SFabien Parent #define CLK_TOP_I2C0 48 6267ea1516SFabien Parent #define CLK_TOP_I2C1 49 6367ea1516SFabien Parent #define CLK_TOP_AUXADC1 50 6467ea1516SFabien Parent #define CLK_TOP_NFI 51 6567ea1516SFabien Parent #define CLK_TOP_NFIECC 52 6667ea1516SFabien Parent #define CLK_TOP_DEBUGSYS 53 6767ea1516SFabien Parent #define CLK_TOP_PWM 54 6867ea1516SFabien Parent #define CLK_TOP_UART0 55 6967ea1516SFabien Parent #define CLK_TOP_UART1 56 7067ea1516SFabien Parent #define CLK_TOP_BTIF 57 7167ea1516SFabien Parent #define CLK_TOP_USB 58 7267ea1516SFabien Parent #define CLK_TOP_FLASHIF_26M 59 7367ea1516SFabien Parent #define CLK_TOP_AUXADC2 60 7467ea1516SFabien Parent #define CLK_TOP_I2C2 61 7567ea1516SFabien Parent #define CLK_TOP_MSDC0 62 7667ea1516SFabien Parent #define CLK_TOP_MSDC1 63 7767ea1516SFabien Parent #define CLK_TOP_NFI2X 64 7867ea1516SFabien Parent #define CLK_TOP_PMICWRAP_AP 65 7967ea1516SFabien Parent #define CLK_TOP_SEJ 66 8067ea1516SFabien Parent #define CLK_TOP_MEMSLP_DLYER 67 8167ea1516SFabien Parent #define CLK_TOP_SPI 68 8267ea1516SFabien Parent #define CLK_TOP_APXGPT 69 8367ea1516SFabien Parent #define CLK_TOP_AUDIO 70 8467ea1516SFabien Parent #define CLK_TOP_PMICWRAP_MD 71 8567ea1516SFabien Parent #define CLK_TOP_PMICWRAP_CONN 72 8667ea1516SFabien Parent #define CLK_TOP_PMICWRAP_26M 73 8767ea1516SFabien Parent #define CLK_TOP_AUX_ADC 74 8867ea1516SFabien Parent #define CLK_TOP_AUX_TP 75 8967ea1516SFabien Parent #define CLK_TOP_MSDC2 76 9067ea1516SFabien Parent #define CLK_TOP_RBIST 77 9167ea1516SFabien Parent #define CLK_TOP_NFI_BUS 78 9267ea1516SFabien Parent #define CLK_TOP_GCE 79 9367ea1516SFabien Parent #define CLK_TOP_TRNG 80 9467ea1516SFabien Parent #define CLK_TOP_SEJ_13M 81 9567ea1516SFabien Parent #define CLK_TOP_AES 82 9667ea1516SFabien Parent #define CLK_TOP_PWM_B 83 9767ea1516SFabien Parent #define CLK_TOP_PWM1_FB 84 9867ea1516SFabien Parent #define CLK_TOP_PWM2_FB 85 9967ea1516SFabien Parent #define CLK_TOP_PWM3_FB 86 10067ea1516SFabien Parent #define CLK_TOP_PWM4_FB 87 10167ea1516SFabien Parent #define CLK_TOP_PWM5_FB 88 10267ea1516SFabien Parent #define CLK_TOP_USB_1P 89 10367ea1516SFabien Parent #define CLK_TOP_FLASHIF_FREERUN 90 10467ea1516SFabien Parent #define CLK_TOP_66M_ETH 91 10567ea1516SFabien Parent #define CLK_TOP_133M_ETH 92 10667ea1516SFabien Parent #define CLK_TOP_FETH_25M 93 10767ea1516SFabien Parent #define CLK_TOP_FETH_50M 94 10867ea1516SFabien Parent #define CLK_TOP_FLASHIF_AXI 95 10967ea1516SFabien Parent #define CLK_TOP_USBIF 96 11067ea1516SFabien Parent #define CLK_TOP_UART2 97 11167ea1516SFabien Parent #define CLK_TOP_BSI 98 11267ea1516SFabien Parent #define CLK_TOP_RG_SPINOR 99 11367ea1516SFabien Parent #define CLK_TOP_RG_MSDC2 100 11467ea1516SFabien Parent #define CLK_TOP_RG_ETH 101 11567ea1516SFabien Parent #define CLK_TOP_RG_AUD1 102 11667ea1516SFabien Parent #define CLK_TOP_RG_AUD2 103 11767ea1516SFabien Parent #define CLK_TOP_RG_AUD_ENGEN1 104 11867ea1516SFabien Parent #define CLK_TOP_RG_AUD_ENGEN2 105 11967ea1516SFabien Parent #define CLK_TOP_RG_I2C 106 12067ea1516SFabien Parent #define CLK_TOP_RG_PWM_INFRA 107 12167ea1516SFabien Parent #define CLK_TOP_RG_AUD_SPDIF_IN 108 12267ea1516SFabien Parent #define CLK_TOP_RG_UART2 109 12367ea1516SFabien Parent #define CLK_TOP_RG_BSI 110 12467ea1516SFabien Parent #define CLK_TOP_RG_DBG_ATCLK 111 12567ea1516SFabien Parent #define CLK_TOP_RG_NFIECC 112 12667ea1516SFabien Parent #define CLK_TOP_RG_APLL1_D2_EN 113 12767ea1516SFabien Parent #define CLK_TOP_RG_APLL1_D4_EN 114 12867ea1516SFabien Parent #define CLK_TOP_RG_APLL1_D8_EN 115 12967ea1516SFabien Parent #define CLK_TOP_RG_APLL2_D2_EN 116 13067ea1516SFabien Parent #define CLK_TOP_RG_APLL2_D4_EN 117 13167ea1516SFabien Parent #define CLK_TOP_RG_APLL2_D8_EN 118 13267ea1516SFabien Parent #define CLK_TOP_APLL12_DIV0 119 13367ea1516SFabien Parent #define CLK_TOP_APLL12_DIV1 120 13467ea1516SFabien Parent #define CLK_TOP_APLL12_DIV2 121 13567ea1516SFabien Parent #define CLK_TOP_APLL12_DIV3 122 13667ea1516SFabien Parent #define CLK_TOP_APLL12_DIV4 123 13767ea1516SFabien Parent #define CLK_TOP_APLL12_DIV4B 124 13867ea1516SFabien Parent #define CLK_TOP_APLL12_DIV5 125 13967ea1516SFabien Parent #define CLK_TOP_APLL12_DIV5B 126 14067ea1516SFabien Parent #define CLK_TOP_APLL12_DIV6 127 14167ea1516SFabien Parent #define CLK_TOP_UART0_SEL 128 14267ea1516SFabien Parent #define CLK_TOP_EMI_DDRPHY_SEL 129 14367ea1516SFabien Parent #define CLK_TOP_AHB_INFRA_SEL 130 14467ea1516SFabien Parent #define CLK_TOP_MSDC0_SEL 131 14567ea1516SFabien Parent #define CLK_TOP_UART1_SEL 132 14667ea1516SFabien Parent #define CLK_TOP_MSDC1_SEL 133 14767ea1516SFabien Parent #define CLK_TOP_PMICSPI_SEL 134 14867ea1516SFabien Parent #define CLK_TOP_QAXI_AUD26M_SEL 135 14967ea1516SFabien Parent #define CLK_TOP_AUD_INTBUS_SEL 136 15067ea1516SFabien Parent #define CLK_TOP_NFI2X_PAD_SEL 137 15167ea1516SFabien Parent #define CLK_TOP_NFI1X_PAD_SEL 138 15267ea1516SFabien Parent #define CLK_TOP_DDRPHYCFG_SEL 139 15367ea1516SFabien Parent #define CLK_TOP_USB_78M_SEL 140 15467ea1516SFabien Parent #define CLK_TOP_SPINOR_SEL 141 15567ea1516SFabien Parent #define CLK_TOP_MSDC2_SEL 142 15667ea1516SFabien Parent #define CLK_TOP_ETH_SEL 143 15767ea1516SFabien Parent #define CLK_TOP_AUD1_SEL 144 15867ea1516SFabien Parent #define CLK_TOP_AUD2_SEL 145 15967ea1516SFabien Parent #define CLK_TOP_AUD_ENGEN1_SEL 146 16067ea1516SFabien Parent #define CLK_TOP_AUD_ENGEN2_SEL 147 16167ea1516SFabien Parent #define CLK_TOP_I2C_SEL 148 16267ea1516SFabien Parent #define CLK_TOP_AUD_I2S0_M_SEL 149 16367ea1516SFabien Parent #define CLK_TOP_AUD_I2S1_M_SEL 150 16467ea1516SFabien Parent #define CLK_TOP_AUD_I2S2_M_SEL 151 16567ea1516SFabien Parent #define CLK_TOP_AUD_I2S3_M_SEL 152 16667ea1516SFabien Parent #define CLK_TOP_AUD_I2S4_M_SEL 153 16767ea1516SFabien Parent #define CLK_TOP_AUD_I2S5_M_SEL 154 16867ea1516SFabien Parent #define CLK_TOP_AUD_SPDIF_B_SEL 155 16967ea1516SFabien Parent #define CLK_TOP_PWM_SEL 156 17067ea1516SFabien Parent #define CLK_TOP_SPI_SEL 157 17167ea1516SFabien Parent #define CLK_TOP_AUD_SPDIFIN_SEL 158 17267ea1516SFabien Parent #define CLK_TOP_UART2_SEL 159 17367ea1516SFabien Parent #define CLK_TOP_BSI_SEL 160 17467ea1516SFabien Parent #define CLK_TOP_DBG_ATCLK_SEL 161 17567ea1516SFabien Parent #define CLK_TOP_CSW_NFIECC_SEL 162 17667ea1516SFabien Parent #define CLK_TOP_NFIECC_SEL 163 17767ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV0 164 17867ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV1 165 17967ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV2 166 18067ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV3 167 18167ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV4 168 18267ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV4B 169 18367ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV5 170 18467ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV5B 171 18567ea1516SFabien Parent #define CLK_TOP_APLL12_CK_DIV6 172 18667ea1516SFabien Parent #define CLK_TOP_USB_78M 173 18767ea1516SFabien Parent #define CLK_TOP_MSDC0_INFRA 174 18867ea1516SFabien Parent #define CLK_TOP_MSDC1_INFRA 175 18967ea1516SFabien Parent #define CLK_TOP_MSDC2_INFRA 176 19067ea1516SFabien Parent #define CLK_TOP_NR_CLK 177 19167ea1516SFabien Parent 19267ea1516SFabien Parent #endif /* _DT_BINDINGS_CLK_MT8516_H */ 193