1*f113a51aSChun-Jie Chen /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*f113a51aSChun-Jie Chen /* 3*f113a51aSChun-Jie Chen * Copyright (c) 2022 MediaTek Inc. 4*f113a51aSChun-Jie Chen * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> 5*f113a51aSChun-Jie Chen */ 6*f113a51aSChun-Jie Chen 7*f113a51aSChun-Jie Chen #ifndef _DT_BINDINGS_CLK_MT8186_H 8*f113a51aSChun-Jie Chen #define _DT_BINDINGS_CLK_MT8186_H 9*f113a51aSChun-Jie Chen 10*f113a51aSChun-Jie Chen /* MCUSYS */ 11*f113a51aSChun-Jie Chen 12*f113a51aSChun-Jie Chen #define CLK_MCU_ARMPLL_LL_SEL 0 13*f113a51aSChun-Jie Chen #define CLK_MCU_ARMPLL_BL_SEL 1 14*f113a51aSChun-Jie Chen #define CLK_MCU_ARMPLL_BUS_SEL 2 15*f113a51aSChun-Jie Chen #define CLK_MCU_NR_CLK 3 16*f113a51aSChun-Jie Chen 17*f113a51aSChun-Jie Chen /* TOPCKGEN */ 18*f113a51aSChun-Jie Chen 19*f113a51aSChun-Jie Chen #define CLK_TOP_AXI 0 20*f113a51aSChun-Jie Chen #define CLK_TOP_SCP 1 21*f113a51aSChun-Jie Chen #define CLK_TOP_MFG 2 22*f113a51aSChun-Jie Chen #define CLK_TOP_CAMTG 3 23*f113a51aSChun-Jie Chen #define CLK_TOP_CAMTG1 4 24*f113a51aSChun-Jie Chen #define CLK_TOP_CAMTG2 5 25*f113a51aSChun-Jie Chen #define CLK_TOP_CAMTG3 6 26*f113a51aSChun-Jie Chen #define CLK_TOP_CAMTG4 7 27*f113a51aSChun-Jie Chen #define CLK_TOP_CAMTG5 8 28*f113a51aSChun-Jie Chen #define CLK_TOP_CAMTG6 9 29*f113a51aSChun-Jie Chen #define CLK_TOP_UART 10 30*f113a51aSChun-Jie Chen #define CLK_TOP_SPI 11 31*f113a51aSChun-Jie Chen #define CLK_TOP_MSDC50_0_HCLK 12 32*f113a51aSChun-Jie Chen #define CLK_TOP_MSDC50_0 13 33*f113a51aSChun-Jie Chen #define CLK_TOP_MSDC30_1 14 34*f113a51aSChun-Jie Chen #define CLK_TOP_AUDIO 15 35*f113a51aSChun-Jie Chen #define CLK_TOP_AUD_INTBUS 16 36*f113a51aSChun-Jie Chen #define CLK_TOP_AUD_1 17 37*f113a51aSChun-Jie Chen #define CLK_TOP_AUD_2 18 38*f113a51aSChun-Jie Chen #define CLK_TOP_AUD_ENGEN1 19 39*f113a51aSChun-Jie Chen #define CLK_TOP_AUD_ENGEN2 20 40*f113a51aSChun-Jie Chen #define CLK_TOP_DISP_PWM 21 41*f113a51aSChun-Jie Chen #define CLK_TOP_SSPM 22 42*f113a51aSChun-Jie Chen #define CLK_TOP_DXCC 23 43*f113a51aSChun-Jie Chen #define CLK_TOP_USB_TOP 24 44*f113a51aSChun-Jie Chen #define CLK_TOP_SRCK 25 45*f113a51aSChun-Jie Chen #define CLK_TOP_SPM 26 46*f113a51aSChun-Jie Chen #define CLK_TOP_I2C 27 47*f113a51aSChun-Jie Chen #define CLK_TOP_PWM 28 48*f113a51aSChun-Jie Chen #define CLK_TOP_SENINF 29 49*f113a51aSChun-Jie Chen #define CLK_TOP_SENINF1 30 50*f113a51aSChun-Jie Chen #define CLK_TOP_SENINF2 31 51*f113a51aSChun-Jie Chen #define CLK_TOP_SENINF3 32 52*f113a51aSChun-Jie Chen #define CLK_TOP_AES_MSDCFDE 33 53*f113a51aSChun-Jie Chen #define CLK_TOP_PWRAP_ULPOSC 34 54*f113a51aSChun-Jie Chen #define CLK_TOP_CAMTM 35 55*f113a51aSChun-Jie Chen #define CLK_TOP_VENC 36 56*f113a51aSChun-Jie Chen #define CLK_TOP_CAM 37 57*f113a51aSChun-Jie Chen #define CLK_TOP_IMG1 38 58*f113a51aSChun-Jie Chen #define CLK_TOP_IPE 39 59*f113a51aSChun-Jie Chen #define CLK_TOP_DPMAIF 40 60*f113a51aSChun-Jie Chen #define CLK_TOP_VDEC 41 61*f113a51aSChun-Jie Chen #define CLK_TOP_DISP 42 62*f113a51aSChun-Jie Chen #define CLK_TOP_MDP 43 63*f113a51aSChun-Jie Chen #define CLK_TOP_AUDIO_H 44 64*f113a51aSChun-Jie Chen #define CLK_TOP_UFS 45 65*f113a51aSChun-Jie Chen #define CLK_TOP_AES_FDE 46 66*f113a51aSChun-Jie Chen #define CLK_TOP_AUDIODSP 47 67*f113a51aSChun-Jie Chen #define CLK_TOP_DVFSRC 48 68*f113a51aSChun-Jie Chen #define CLK_TOP_DSI_OCC 49 69*f113a51aSChun-Jie Chen #define CLK_TOP_SPMI_MST 50 70*f113a51aSChun-Jie Chen #define CLK_TOP_SPINOR 51 71*f113a51aSChun-Jie Chen #define CLK_TOP_NNA 52 72*f113a51aSChun-Jie Chen #define CLK_TOP_NNA1 53 73*f113a51aSChun-Jie Chen #define CLK_TOP_NNA2 54 74*f113a51aSChun-Jie Chen #define CLK_TOP_SSUSB_XHCI 55 75*f113a51aSChun-Jie Chen #define CLK_TOP_SSUSB_TOP_1P 56 76*f113a51aSChun-Jie Chen #define CLK_TOP_SSUSB_XHCI_1P 57 77*f113a51aSChun-Jie Chen #define CLK_TOP_WPE 58 78*f113a51aSChun-Jie Chen #define CLK_TOP_DPI 59 79*f113a51aSChun-Jie Chen #define CLK_TOP_U3_OCC_250M 60 80*f113a51aSChun-Jie Chen #define CLK_TOP_U3_OCC_500M 61 81*f113a51aSChun-Jie Chen #define CLK_TOP_ADSP_BUS 62 82*f113a51aSChun-Jie Chen #define CLK_TOP_APLL_I2S0_MCK_SEL 63 83*f113a51aSChun-Jie Chen #define CLK_TOP_APLL_I2S1_MCK_SEL 64 84*f113a51aSChun-Jie Chen #define CLK_TOP_APLL_I2S2_MCK_SEL 65 85*f113a51aSChun-Jie Chen #define CLK_TOP_APLL_I2S4_MCK_SEL 66 86*f113a51aSChun-Jie Chen #define CLK_TOP_APLL_TDMOUT_MCK_SEL 67 87*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D2 68 88*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D2_D2 69 89*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D2_D4 70 90*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D2_D16 71 91*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D3 72 92*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D3_D2 73 93*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D3_D4 74 94*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D5 75 95*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D5_D2 76 96*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D5_D4 77 97*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D7 78 98*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D7_D2 79 99*f113a51aSChun-Jie Chen #define CLK_TOP_MAINPLL_D7_D4 80 100*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL 81 101*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D2 82 102*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D2_D2 83 103*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D2_D4 84 104*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D3 85 105*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D3_D2 86 106*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D3_D4 87 107*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D3_D8 88 108*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D3_D32 89 109*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D5 90 110*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D5_D2 91 111*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D5_D4 92 112*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_D7 93 113*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_192M 94 114*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_192M_D4 95 115*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_192M_D8 96 116*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_192M_D16 97 117*f113a51aSChun-Jie Chen #define CLK_TOP_UNIVPLL_192M_D32 98 118*f113a51aSChun-Jie Chen #define CLK_TOP_APLL1_D2 99 119*f113a51aSChun-Jie Chen #define CLK_TOP_APLL1_D4 100 120*f113a51aSChun-Jie Chen #define CLK_TOP_APLL1_D8 101 121*f113a51aSChun-Jie Chen #define CLK_TOP_APLL2_D2 102 122*f113a51aSChun-Jie Chen #define CLK_TOP_APLL2_D4 103 123*f113a51aSChun-Jie Chen #define CLK_TOP_APLL2_D8 104 124*f113a51aSChun-Jie Chen #define CLK_TOP_MMPLL_D2 105 125*f113a51aSChun-Jie Chen #define CLK_TOP_TVDPLL_D2 106 126*f113a51aSChun-Jie Chen #define CLK_TOP_TVDPLL_D4 107 127*f113a51aSChun-Jie Chen #define CLK_TOP_TVDPLL_D8 108 128*f113a51aSChun-Jie Chen #define CLK_TOP_TVDPLL_D16 109 129*f113a51aSChun-Jie Chen #define CLK_TOP_TVDPLL_D32 110 130*f113a51aSChun-Jie Chen #define CLK_TOP_MSDCPLL_D2 111 131*f113a51aSChun-Jie Chen #define CLK_TOP_ULPOSC1 112 132*f113a51aSChun-Jie Chen #define CLK_TOP_ULPOSC1_D2 113 133*f113a51aSChun-Jie Chen #define CLK_TOP_ULPOSC1_D4 114 134*f113a51aSChun-Jie Chen #define CLK_TOP_ULPOSC1_D8 115 135*f113a51aSChun-Jie Chen #define CLK_TOP_ULPOSC1_D10 116 136*f113a51aSChun-Jie Chen #define CLK_TOP_ULPOSC1_D16 117 137*f113a51aSChun-Jie Chen #define CLK_TOP_ULPOSC1_D32 118 138*f113a51aSChun-Jie Chen #define CLK_TOP_ADSPPLL_D2 119 139*f113a51aSChun-Jie Chen #define CLK_TOP_ADSPPLL_D4 120 140*f113a51aSChun-Jie Chen #define CLK_TOP_ADSPPLL_D8 121 141*f113a51aSChun-Jie Chen #define CLK_TOP_NNAPLL_D2 122 142*f113a51aSChun-Jie Chen #define CLK_TOP_NNAPLL_D4 123 143*f113a51aSChun-Jie Chen #define CLK_TOP_NNAPLL_D8 124 144*f113a51aSChun-Jie Chen #define CLK_TOP_NNA2PLL_D2 125 145*f113a51aSChun-Jie Chen #define CLK_TOP_NNA2PLL_D4 126 146*f113a51aSChun-Jie Chen #define CLK_TOP_NNA2PLL_D8 127 147*f113a51aSChun-Jie Chen #define CLK_TOP_F_BIST2FPC 128 148*f113a51aSChun-Jie Chen #define CLK_TOP_466M_FMEM 129 149*f113a51aSChun-Jie Chen #define CLK_TOP_MPLL 130 150*f113a51aSChun-Jie Chen #define CLK_TOP_APLL12_CK_DIV0 131 151*f113a51aSChun-Jie Chen #define CLK_TOP_APLL12_CK_DIV1 132 152*f113a51aSChun-Jie Chen #define CLK_TOP_APLL12_CK_DIV2 133 153*f113a51aSChun-Jie Chen #define CLK_TOP_APLL12_CK_DIV4 134 154*f113a51aSChun-Jie Chen #define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 135 155*f113a51aSChun-Jie Chen #define CLK_TOP_NR_CLK 136 156*f113a51aSChun-Jie Chen 157*f113a51aSChun-Jie Chen /* INFRACFG_AO */ 158*f113a51aSChun-Jie Chen 159*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PMIC_TMR 0 160*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PMIC_AP 1 161*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PMIC_MD 2 162*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PMIC_CONN 3 163*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SCP_CORE 4 164*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SEJ 5 165*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_APXGPT 6 166*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_ICUSB 7 167*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_GCE 8 168*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_THERM 9 169*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C_AP 10 170*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C_CCU 11 171*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C_SSPM 12 172*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C_RSV 13 173*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PWM_HCLK 14 174*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PWM1 15 175*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PWM2 16 176*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PWM3 17 177*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PWM4 18 178*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PWM5 19 179*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_PWM 20 180*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_UART0 21 181*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_UART1 22 182*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_UART2 23 183*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_GCE_26M 24 184*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CQ_DMA_FPC 25 185*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_BTIF 26 186*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SPI0 27 187*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MSDC0 28 188*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MSDCFDE 29 189*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MSDC1 30 190*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_DVFSRC 31 191*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_GCPU 32 192*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_TRNG 33 193*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_AUXADC 34 194*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CPUM 35 195*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF1_AP 36 196*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF1_MD 37 197*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_AUXADC_MD 38 198*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_AP_DMA 39 199*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_XIU 40 200*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_DEVICE_APC 41 201*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF_AP 42 202*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_DEBUGTOP 43 203*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_AUDIO 44 204*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF_MD 45 205*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_DXCC_SEC_CORE 46 206*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_DXCC_AO 47 207*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_IMP_IIC 48 208*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_DRAMC_F26M 49 209*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_RG_PWM_FBCLK6 50 210*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSUSB_TOP_HCLK 51 211*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_DISP_PWM 52 212*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CLDMA_BCLK 53 213*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_AUDIO_26M_BCLK 54 214*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK 55 215*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SPI1 56 216*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C4 57 217*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MODEM_TEMP_SHARE 58 218*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SPI2 59 219*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SPI3 60 220*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSUSB_TOP_REF 61 221*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSUSB_TOP_XHCI 62 222*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSUSB_TOP_P1_REF 63 223*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI 64 224*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSPM 65 225*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSUSB_TOP_P1_SYS 66 226*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C5 67 227*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C5_ARBITER 68 228*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C5_IMM 69 229*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C1_ARBITER 70 230*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C1_IMM 71 231*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C2_ARBITER 72 232*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C2_IMM 73 233*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SPI4 74 234*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SPI5 75 235*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CQ_DMA 76 236*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_BIST2FPC 77 237*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MSDC0_SELF 78 238*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SPINOR 79 239*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSPM_26M_SELF 80 240*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SSPM_32K_SELF 81 241*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_I2C6 82 242*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_AP_MSDC0 83 243*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MD_MSDC0 84 244*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MSDC0_SRC 85 245*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MSDC1_SRC 86 246*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_SEJ_F13M 87 247*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_AES_TOP0_BCLK 88 248*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_MCU_PM_BCLK 89 249*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF2_AP 90 250*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF2_MD 91 251*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF3_AP 92 252*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF3_MD 93 253*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_FADSP_26M 94 254*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_FADSP_32K 95 255*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF4_AP 96 256*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_CCIF4_MD 97 257*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_FADSP 98 258*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_FLASHIF_133M 99 259*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_FLASHIF_66M 100 260*f113a51aSChun-Jie Chen #define CLK_INFRA_AO_NR_CLK 101 261*f113a51aSChun-Jie Chen 262*f113a51aSChun-Jie Chen /* APMIXEDSYS */ 263*f113a51aSChun-Jie Chen 264*f113a51aSChun-Jie Chen #define CLK_APMIXED_ARMPLL_LL 0 265*f113a51aSChun-Jie Chen #define CLK_APMIXED_ARMPLL_BL 1 266*f113a51aSChun-Jie Chen #define CLK_APMIXED_CCIPLL 2 267*f113a51aSChun-Jie Chen #define CLK_APMIXED_MAINPLL 3 268*f113a51aSChun-Jie Chen #define CLK_APMIXED_UNIV2PLL 4 269*f113a51aSChun-Jie Chen #define CLK_APMIXED_MSDCPLL 5 270*f113a51aSChun-Jie Chen #define CLK_APMIXED_MMPLL 6 271*f113a51aSChun-Jie Chen #define CLK_APMIXED_NNAPLL 7 272*f113a51aSChun-Jie Chen #define CLK_APMIXED_NNA2PLL 8 273*f113a51aSChun-Jie Chen #define CLK_APMIXED_ADSPPLL 9 274*f113a51aSChun-Jie Chen #define CLK_APMIXED_MFGPLL 10 275*f113a51aSChun-Jie Chen #define CLK_APMIXED_TVDPLL 11 276*f113a51aSChun-Jie Chen #define CLK_APMIXED_APLL1 12 277*f113a51aSChun-Jie Chen #define CLK_APMIXED_APLL2 13 278*f113a51aSChun-Jie Chen #define CLK_APMIXED_NR_CLK 14 279*f113a51aSChun-Jie Chen 280*f113a51aSChun-Jie Chen /* IMP_IIC_WRAP */ 281*f113a51aSChun-Jie Chen 282*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0 0 283*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1 1 284*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2 2 285*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3 3 286*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4 4 287*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5 5 288*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6 6 289*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7 7 290*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8 8 291*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9 9 292*f113a51aSChun-Jie Chen #define CLK_IMP_IIC_WRAP_NR_CLK 10 293*f113a51aSChun-Jie Chen 294*f113a51aSChun-Jie Chen /* MFGCFG */ 295*f113a51aSChun-Jie Chen 296*f113a51aSChun-Jie Chen #define CLK_MFG_BG3D 0 297*f113a51aSChun-Jie Chen #define CLK_MFG_NR_CLK 1 298*f113a51aSChun-Jie Chen 299*f113a51aSChun-Jie Chen /* MMSYS */ 300*f113a51aSChun-Jie Chen 301*f113a51aSChun-Jie Chen #define CLK_MM_DISP_MUTEX0 0 302*f113a51aSChun-Jie Chen #define CLK_MM_APB_MM_BUS 1 303*f113a51aSChun-Jie Chen #define CLK_MM_DISP_OVL0 2 304*f113a51aSChun-Jie Chen #define CLK_MM_DISP_RDMA0 3 305*f113a51aSChun-Jie Chen #define CLK_MM_DISP_OVL0_2L 4 306*f113a51aSChun-Jie Chen #define CLK_MM_DISP_WDMA0 5 307*f113a51aSChun-Jie Chen #define CLK_MM_DISP_RSZ0 6 308*f113a51aSChun-Jie Chen #define CLK_MM_DISP_AAL0 7 309*f113a51aSChun-Jie Chen #define CLK_MM_DISP_CCORR0 8 310*f113a51aSChun-Jie Chen #define CLK_MM_DISP_COLOR0 9 311*f113a51aSChun-Jie Chen #define CLK_MM_SMI_INFRA 10 312*f113a51aSChun-Jie Chen #define CLK_MM_DISP_DSC_WRAP0 11 313*f113a51aSChun-Jie Chen #define CLK_MM_DISP_GAMMA0 12 314*f113a51aSChun-Jie Chen #define CLK_MM_DISP_POSTMASK0 13 315*f113a51aSChun-Jie Chen #define CLK_MM_DISP_DITHER0 14 316*f113a51aSChun-Jie Chen #define CLK_MM_SMI_COMMON 15 317*f113a51aSChun-Jie Chen #define CLK_MM_DSI0 16 318*f113a51aSChun-Jie Chen #define CLK_MM_DISP_FAKE_ENG0 17 319*f113a51aSChun-Jie Chen #define CLK_MM_DISP_FAKE_ENG1 18 320*f113a51aSChun-Jie Chen #define CLK_MM_SMI_GALS 19 321*f113a51aSChun-Jie Chen #define CLK_MM_SMI_IOMMU 20 322*f113a51aSChun-Jie Chen #define CLK_MM_DISP_RDMA1 21 323*f113a51aSChun-Jie Chen #define CLK_MM_DISP_DPI 22 324*f113a51aSChun-Jie Chen #define CLK_MM_DSI0_DSI_CK_DOMAIN 23 325*f113a51aSChun-Jie Chen #define CLK_MM_DISP_26M 24 326*f113a51aSChun-Jie Chen #define CLK_MM_NR_CLK 25 327*f113a51aSChun-Jie Chen 328*f113a51aSChun-Jie Chen /* WPESYS */ 329*f113a51aSChun-Jie Chen 330*f113a51aSChun-Jie Chen #define CLK_WPE_CK_EN 0 331*f113a51aSChun-Jie Chen #define CLK_WPE_SMI_LARB8_CK_EN 1 332*f113a51aSChun-Jie Chen #define CLK_WPE_SYS_EVENT_TX_CK_EN 2 333*f113a51aSChun-Jie Chen #define CLK_WPE_SMI_LARB8_PCLK_EN 3 334*f113a51aSChun-Jie Chen #define CLK_WPE_NR_CLK 4 335*f113a51aSChun-Jie Chen 336*f113a51aSChun-Jie Chen /* IMGSYS1 */ 337*f113a51aSChun-Jie Chen 338*f113a51aSChun-Jie Chen #define CLK_IMG1_LARB9_IMG1 0 339*f113a51aSChun-Jie Chen #define CLK_IMG1_LARB10_IMG1 1 340*f113a51aSChun-Jie Chen #define CLK_IMG1_DIP 2 341*f113a51aSChun-Jie Chen #define CLK_IMG1_GALS_IMG1 3 342*f113a51aSChun-Jie Chen #define CLK_IMG1_NR_CLK 4 343*f113a51aSChun-Jie Chen 344*f113a51aSChun-Jie Chen /* IMGSYS2 */ 345*f113a51aSChun-Jie Chen 346*f113a51aSChun-Jie Chen #define CLK_IMG2_LARB9_IMG2 0 347*f113a51aSChun-Jie Chen #define CLK_IMG2_LARB10_IMG2 1 348*f113a51aSChun-Jie Chen #define CLK_IMG2_MFB 2 349*f113a51aSChun-Jie Chen #define CLK_IMG2_WPE 3 350*f113a51aSChun-Jie Chen #define CLK_IMG2_MSS 4 351*f113a51aSChun-Jie Chen #define CLK_IMG2_GALS_IMG2 5 352*f113a51aSChun-Jie Chen #define CLK_IMG2_NR_CLK 6 353*f113a51aSChun-Jie Chen 354*f113a51aSChun-Jie Chen /* VDECSYS */ 355*f113a51aSChun-Jie Chen 356*f113a51aSChun-Jie Chen #define CLK_VDEC_LARB1_CKEN 0 357*f113a51aSChun-Jie Chen #define CLK_VDEC_LAT_CKEN 1 358*f113a51aSChun-Jie Chen #define CLK_VDEC_LAT_ACTIVE 2 359*f113a51aSChun-Jie Chen #define CLK_VDEC_LAT_CKEN_ENG 3 360*f113a51aSChun-Jie Chen #define CLK_VDEC_MINI_MDP_CKEN_CFG_RG 4 361*f113a51aSChun-Jie Chen #define CLK_VDEC_CKEN 5 362*f113a51aSChun-Jie Chen #define CLK_VDEC_ACTIVE 6 363*f113a51aSChun-Jie Chen #define CLK_VDEC_CKEN_ENG 7 364*f113a51aSChun-Jie Chen #define CLK_VDEC_NR_CLK 8 365*f113a51aSChun-Jie Chen 366*f113a51aSChun-Jie Chen /* VENCSYS */ 367*f113a51aSChun-Jie Chen 368*f113a51aSChun-Jie Chen #define CLK_VENC_CKE0_LARB 0 369*f113a51aSChun-Jie Chen #define CLK_VENC_CKE1_VENC 1 370*f113a51aSChun-Jie Chen #define CLK_VENC_CKE2_JPGENC 2 371*f113a51aSChun-Jie Chen #define CLK_VENC_CKE5_GALS 3 372*f113a51aSChun-Jie Chen #define CLK_VENC_NR_CLK 4 373*f113a51aSChun-Jie Chen 374*f113a51aSChun-Jie Chen /* CAMSYS */ 375*f113a51aSChun-Jie Chen 376*f113a51aSChun-Jie Chen #define CLK_CAM_LARB13 0 377*f113a51aSChun-Jie Chen #define CLK_CAM_DFP_VAD 1 378*f113a51aSChun-Jie Chen #define CLK_CAM_LARB14 2 379*f113a51aSChun-Jie Chen #define CLK_CAM 3 380*f113a51aSChun-Jie Chen #define CLK_CAMTG 4 381*f113a51aSChun-Jie Chen #define CLK_CAM_SENINF 5 382*f113a51aSChun-Jie Chen #define CLK_CAMSV1 6 383*f113a51aSChun-Jie Chen #define CLK_CAMSV2 7 384*f113a51aSChun-Jie Chen #define CLK_CAMSV3 8 385*f113a51aSChun-Jie Chen #define CLK_CAM_CCU0 9 386*f113a51aSChun-Jie Chen #define CLK_CAM_CCU1 10 387*f113a51aSChun-Jie Chen #define CLK_CAM_MRAW0 11 388*f113a51aSChun-Jie Chen #define CLK_CAM_FAKE_ENG 12 389*f113a51aSChun-Jie Chen #define CLK_CAM_CCU_GALS 13 390*f113a51aSChun-Jie Chen #define CLK_CAM2MM_GALS 14 391*f113a51aSChun-Jie Chen #define CLK_CAM_NR_CLK 15 392*f113a51aSChun-Jie Chen 393*f113a51aSChun-Jie Chen /* CAMSYS_RAWA */ 394*f113a51aSChun-Jie Chen 395*f113a51aSChun-Jie Chen #define CLK_CAM_RAWA_LARBX_RAWA 0 396*f113a51aSChun-Jie Chen #define CLK_CAM_RAWA 1 397*f113a51aSChun-Jie Chen #define CLK_CAM_RAWA_CAMTG_RAWA 2 398*f113a51aSChun-Jie Chen #define CLK_CAM_RAWA_NR_CLK 3 399*f113a51aSChun-Jie Chen 400*f113a51aSChun-Jie Chen /* CAMSYS_RAWB */ 401*f113a51aSChun-Jie Chen 402*f113a51aSChun-Jie Chen #define CLK_CAM_RAWB_LARBX_RAWB 0 403*f113a51aSChun-Jie Chen #define CLK_CAM_RAWB 1 404*f113a51aSChun-Jie Chen #define CLK_CAM_RAWB_CAMTG_RAWB 2 405*f113a51aSChun-Jie Chen #define CLK_CAM_RAWB_NR_CLK 3 406*f113a51aSChun-Jie Chen 407*f113a51aSChun-Jie Chen /* MDPSYS */ 408*f113a51aSChun-Jie Chen 409*f113a51aSChun-Jie Chen #define CLK_MDP_RDMA0 0 410*f113a51aSChun-Jie Chen #define CLK_MDP_TDSHP0 1 411*f113a51aSChun-Jie Chen #define CLK_MDP_IMG_DL_ASYNC0 2 412*f113a51aSChun-Jie Chen #define CLK_MDP_IMG_DL_ASYNC1 3 413*f113a51aSChun-Jie Chen #define CLK_MDP_DISP_RDMA 4 414*f113a51aSChun-Jie Chen #define CLK_MDP_HMS 5 415*f113a51aSChun-Jie Chen #define CLK_MDP_SMI0 6 416*f113a51aSChun-Jie Chen #define CLK_MDP_APB_BUS 7 417*f113a51aSChun-Jie Chen #define CLK_MDP_WROT0 8 418*f113a51aSChun-Jie Chen #define CLK_MDP_RSZ0 9 419*f113a51aSChun-Jie Chen #define CLK_MDP_HDR0 10 420*f113a51aSChun-Jie Chen #define CLK_MDP_MUTEX0 11 421*f113a51aSChun-Jie Chen #define CLK_MDP_WROT1 12 422*f113a51aSChun-Jie Chen #define CLK_MDP_RSZ1 13 423*f113a51aSChun-Jie Chen #define CLK_MDP_FAKE_ENG0 14 424*f113a51aSChun-Jie Chen #define CLK_MDP_AAL0 15 425*f113a51aSChun-Jie Chen #define CLK_MDP_DISP_WDMA 16 426*f113a51aSChun-Jie Chen #define CLK_MDP_COLOR 17 427*f113a51aSChun-Jie Chen #define CLK_MDP_IMG_DL_ASYNC2 18 428*f113a51aSChun-Jie Chen #define CLK_MDP_IMG_DL_RELAY0_ASYNC0 19 429*f113a51aSChun-Jie Chen #define CLK_MDP_IMG_DL_RELAY1_ASYNC1 20 430*f113a51aSChun-Jie Chen #define CLK_MDP_IMG_DL_RELAY2_ASYNC2 21 431*f113a51aSChun-Jie Chen #define CLK_MDP_NR_CLK 22 432*f113a51aSChun-Jie Chen 433*f113a51aSChun-Jie Chen /* IPESYS */ 434*f113a51aSChun-Jie Chen 435*f113a51aSChun-Jie Chen #define CLK_IPE_LARB19 0 436*f113a51aSChun-Jie Chen #define CLK_IPE_LARB20 1 437*f113a51aSChun-Jie Chen #define CLK_IPE_SMI_SUBCOM 2 438*f113a51aSChun-Jie Chen #define CLK_IPE_FD 3 439*f113a51aSChun-Jie Chen #define CLK_IPE_FE 4 440*f113a51aSChun-Jie Chen #define CLK_IPE_RSC 5 441*f113a51aSChun-Jie Chen #define CLK_IPE_DPE 6 442*f113a51aSChun-Jie Chen #define CLK_IPE_GALS_IPE 7 443*f113a51aSChun-Jie Chen #define CLK_IPE_NR_CLK 8 444*f113a51aSChun-Jie Chen 445*f113a51aSChun-Jie Chen #endif /* _DT_BINDINGS_CLK_MT8186_H */ 446