1c1e81a3bSJames Liao /* 2c1e81a3bSJames Liao * Copyright (c) 2014 MediaTek Inc. 3c1e81a3bSJames Liao * Author: James Liao <jamesjj.liao@mediatek.com> 4c1e81a3bSJames Liao * 5c1e81a3bSJames Liao * This program is free software; you can redistribute it and/or modify 6c1e81a3bSJames Liao * it under the terms of the GNU General Public License version 2 as 7c1e81a3bSJames Liao * published by the Free Software Foundation. 8c1e81a3bSJames Liao * 9c1e81a3bSJames Liao * This program is distributed in the hope that it will be useful, 10c1e81a3bSJames Liao * but WITHOUT ANY WARRANTY; without even the implied warranty of 11c1e81a3bSJames Liao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12c1e81a3bSJames Liao * GNU General Public License for more details. 13c1e81a3bSJames Liao */ 14c1e81a3bSJames Liao 15c1e81a3bSJames Liao #ifndef _DT_BINDINGS_CLK_MT8173_H 16c1e81a3bSJames Liao #define _DT_BINDINGS_CLK_MT8173_H 17c1e81a3bSJames Liao 18c1e81a3bSJames Liao /* TOPCKGEN */ 19c1e81a3bSJames Liao 20c1e81a3bSJames Liao #define CLK_TOP_CLKPH_MCK_O 1 21c1e81a3bSJames Liao #define CLK_TOP_USB_SYSPLL_125M 3 22c1e81a3bSJames Liao #define CLK_TOP_HDMITX_DIG_CTS 4 23c1e81a3bSJames Liao #define CLK_TOP_ARMCA7PLL_754M 5 24c1e81a3bSJames Liao #define CLK_TOP_ARMCA7PLL_502M 6 25c1e81a3bSJames Liao #define CLK_TOP_MAIN_H546M 7 26c1e81a3bSJames Liao #define CLK_TOP_MAIN_H364M 8 27c1e81a3bSJames Liao #define CLK_TOP_MAIN_H218P4M 9 28c1e81a3bSJames Liao #define CLK_TOP_MAIN_H156M 10 29c1e81a3bSJames Liao #define CLK_TOP_TVDPLL_445P5M 11 30c1e81a3bSJames Liao #define CLK_TOP_TVDPLL_594M 12 31c1e81a3bSJames Liao #define CLK_TOP_UNIV_624M 13 32c1e81a3bSJames Liao #define CLK_TOP_UNIV_416M 14 33c1e81a3bSJames Liao #define CLK_TOP_UNIV_249P6M 15 34c1e81a3bSJames Liao #define CLK_TOP_UNIV_178P3M 16 35c1e81a3bSJames Liao #define CLK_TOP_UNIV_48M 17 36c1e81a3bSJames Liao #define CLK_TOP_CLKRTC_EXT 18 37c1e81a3bSJames Liao #define CLK_TOP_CLKRTC_INT 19 38c1e81a3bSJames Liao #define CLK_TOP_FPC 20 39c1e81a3bSJames Liao #define CLK_TOP_HDMITXPLL_D2 21 40c1e81a3bSJames Liao #define CLK_TOP_HDMITXPLL_D3 22 41c1e81a3bSJames Liao #define CLK_TOP_ARMCA7PLL_D2 23 42c1e81a3bSJames Liao #define CLK_TOP_ARMCA7PLL_D3 24 43c1e81a3bSJames Liao #define CLK_TOP_APLL1 25 44c1e81a3bSJames Liao #define CLK_TOP_APLL2 26 45c1e81a3bSJames Liao #define CLK_TOP_DMPLL 27 46c1e81a3bSJames Liao #define CLK_TOP_DMPLL_D2 28 47c1e81a3bSJames Liao #define CLK_TOP_DMPLL_D4 29 48c1e81a3bSJames Liao #define CLK_TOP_DMPLL_D8 30 49c1e81a3bSJames Liao #define CLK_TOP_DMPLL_D16 31 50c1e81a3bSJames Liao #define CLK_TOP_LVDSPLL_D2 32 51c1e81a3bSJames Liao #define CLK_TOP_LVDSPLL_D4 33 52c1e81a3bSJames Liao #define CLK_TOP_LVDSPLL_D8 34 53c1e81a3bSJames Liao #define CLK_TOP_MMPLL 35 54c1e81a3bSJames Liao #define CLK_TOP_MMPLL_D2 36 55c1e81a3bSJames Liao #define CLK_TOP_MSDCPLL 37 56c1e81a3bSJames Liao #define CLK_TOP_MSDCPLL_D2 38 57c1e81a3bSJames Liao #define CLK_TOP_MSDCPLL_D4 39 58c1e81a3bSJames Liao #define CLK_TOP_MSDCPLL2 40 59c1e81a3bSJames Liao #define CLK_TOP_MSDCPLL2_D2 41 60c1e81a3bSJames Liao #define CLK_TOP_MSDCPLL2_D4 42 61c1e81a3bSJames Liao #define CLK_TOP_SYSPLL_D2 43 62c1e81a3bSJames Liao #define CLK_TOP_SYSPLL1_D2 44 63c1e81a3bSJames Liao #define CLK_TOP_SYSPLL1_D4 45 64c1e81a3bSJames Liao #define CLK_TOP_SYSPLL1_D8 46 65c1e81a3bSJames Liao #define CLK_TOP_SYSPLL1_D16 47 66c1e81a3bSJames Liao #define CLK_TOP_SYSPLL_D3 48 67c1e81a3bSJames Liao #define CLK_TOP_SYSPLL2_D2 49 68c1e81a3bSJames Liao #define CLK_TOP_SYSPLL2_D4 50 69c1e81a3bSJames Liao #define CLK_TOP_SYSPLL_D5 51 70c1e81a3bSJames Liao #define CLK_TOP_SYSPLL3_D2 52 71c1e81a3bSJames Liao #define CLK_TOP_SYSPLL3_D4 53 72c1e81a3bSJames Liao #define CLK_TOP_SYSPLL_D7 54 73c1e81a3bSJames Liao #define CLK_TOP_SYSPLL4_D2 55 74c1e81a3bSJames Liao #define CLK_TOP_SYSPLL4_D4 56 75c1e81a3bSJames Liao #define CLK_TOP_TVDPLL 57 76c1e81a3bSJames Liao #define CLK_TOP_TVDPLL_D2 58 77c1e81a3bSJames Liao #define CLK_TOP_TVDPLL_D4 59 78c1e81a3bSJames Liao #define CLK_TOP_TVDPLL_D8 60 79c1e81a3bSJames Liao #define CLK_TOP_TVDPLL_D16 61 80c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL_D2 62 81c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL1_D2 63 82c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL1_D4 64 83c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL1_D8 65 84c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL_D3 66 85c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL2_D2 67 86c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL2_D4 68 87c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL2_D8 69 88c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL_D5 70 89c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL3_D2 71 90c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL3_D4 72 91c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL3_D8 73 92c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL_D7 74 93c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL_D26 75 94c1e81a3bSJames Liao #define CLK_TOP_UNIVPLL_D52 76 95c1e81a3bSJames Liao #define CLK_TOP_VCODECPLL 77 96c1e81a3bSJames Liao #define CLK_TOP_VCODECPLL_370P5 78 97c1e81a3bSJames Liao #define CLK_TOP_VENCPLL 79 98c1e81a3bSJames Liao #define CLK_TOP_VENCPLL_D2 80 99c1e81a3bSJames Liao #define CLK_TOP_VENCPLL_D4 81 100c1e81a3bSJames Liao #define CLK_TOP_AXI_SEL 82 101c1e81a3bSJames Liao #define CLK_TOP_MEM_SEL 83 102c1e81a3bSJames Liao #define CLK_TOP_DDRPHYCFG_SEL 84 103c1e81a3bSJames Liao #define CLK_TOP_MM_SEL 85 104c1e81a3bSJames Liao #define CLK_TOP_PWM_SEL 86 105c1e81a3bSJames Liao #define CLK_TOP_VDEC_SEL 87 106c1e81a3bSJames Liao #define CLK_TOP_VENC_SEL 88 107c1e81a3bSJames Liao #define CLK_TOP_MFG_SEL 89 108c1e81a3bSJames Liao #define CLK_TOP_CAMTG_SEL 90 109c1e81a3bSJames Liao #define CLK_TOP_UART_SEL 91 110c1e81a3bSJames Liao #define CLK_TOP_SPI_SEL 92 111c1e81a3bSJames Liao #define CLK_TOP_USB20_SEL 93 112c1e81a3bSJames Liao #define CLK_TOP_USB30_SEL 94 113c1e81a3bSJames Liao #define CLK_TOP_MSDC50_0_H_SEL 95 114c1e81a3bSJames Liao #define CLK_TOP_MSDC50_0_SEL 96 115c1e81a3bSJames Liao #define CLK_TOP_MSDC30_1_SEL 97 116c1e81a3bSJames Liao #define CLK_TOP_MSDC30_2_SEL 98 117c1e81a3bSJames Liao #define CLK_TOP_MSDC30_3_SEL 99 118c1e81a3bSJames Liao #define CLK_TOP_AUDIO_SEL 100 119c1e81a3bSJames Liao #define CLK_TOP_AUD_INTBUS_SEL 101 120c1e81a3bSJames Liao #define CLK_TOP_PMICSPI_SEL 102 121c1e81a3bSJames Liao #define CLK_TOP_SCP_SEL 103 122c1e81a3bSJames Liao #define CLK_TOP_ATB_SEL 104 123c1e81a3bSJames Liao #define CLK_TOP_VENC_LT_SEL 105 124c1e81a3bSJames Liao #define CLK_TOP_DPI0_SEL 106 125c1e81a3bSJames Liao #define CLK_TOP_IRDA_SEL 107 126c1e81a3bSJames Liao #define CLK_TOP_CCI400_SEL 108 127c1e81a3bSJames Liao #define CLK_TOP_AUD_1_SEL 109 128c1e81a3bSJames Liao #define CLK_TOP_AUD_2_SEL 110 129c1e81a3bSJames Liao #define CLK_TOP_MEM_MFG_IN_SEL 111 130c1e81a3bSJames Liao #define CLK_TOP_AXI_MFG_IN_SEL 112 131c1e81a3bSJames Liao #define CLK_TOP_SCAM_SEL 113 132c1e81a3bSJames Liao #define CLK_TOP_SPINFI_IFR_SEL 114 133c1e81a3bSJames Liao #define CLK_TOP_HDMI_SEL 115 134c1e81a3bSJames Liao #define CLK_TOP_DPILVDS_SEL 116 135c1e81a3bSJames Liao #define CLK_TOP_MSDC50_2_H_SEL 117 136c1e81a3bSJames Liao #define CLK_TOP_HDCP_SEL 118 137c1e81a3bSJames Liao #define CLK_TOP_HDCP_24M_SEL 119 138c1e81a3bSJames Liao #define CLK_TOP_RTC_SEL 120 139c1e81a3bSJames Liao #define CLK_TOP_APLL1_DIV0 121 140c1e81a3bSJames Liao #define CLK_TOP_APLL1_DIV1 122 141c1e81a3bSJames Liao #define CLK_TOP_APLL1_DIV2 123 142c1e81a3bSJames Liao #define CLK_TOP_APLL1_DIV3 124 143c1e81a3bSJames Liao #define CLK_TOP_APLL1_DIV4 125 144c1e81a3bSJames Liao #define CLK_TOP_APLL1_DIV5 126 145c1e81a3bSJames Liao #define CLK_TOP_APLL2_DIV0 127 146c1e81a3bSJames Liao #define CLK_TOP_APLL2_DIV1 128 147c1e81a3bSJames Liao #define CLK_TOP_APLL2_DIV2 129 148c1e81a3bSJames Liao #define CLK_TOP_APLL2_DIV3 130 149c1e81a3bSJames Liao #define CLK_TOP_APLL2_DIV4 131 150c1e81a3bSJames Liao #define CLK_TOP_APLL2_DIV5 132 151c1e81a3bSJames Liao #define CLK_TOP_I2S0_M_SEL 133 152c1e81a3bSJames Liao #define CLK_TOP_I2S1_M_SEL 134 153c1e81a3bSJames Liao #define CLK_TOP_I2S2_M_SEL 135 154c1e81a3bSJames Liao #define CLK_TOP_I2S3_M_SEL 136 155c1e81a3bSJames Liao #define CLK_TOP_I2S3_B_SEL 137 15629859d93SJames Liao #define CLK_TOP_DSI0_DIG 138 15729859d93SJames Liao #define CLK_TOP_DSI1_DIG 139 15829859d93SJames Liao #define CLK_TOP_LVDS_PXL 140 15929859d93SJames Liao #define CLK_TOP_LVDS_CTS 141 16029859d93SJames Liao #define CLK_TOP_NR_CLK 142 161c1e81a3bSJames Liao 162c1e81a3bSJames Liao /* APMIXED_SYS */ 163c1e81a3bSJames Liao 164c1e81a3bSJames Liao #define CLK_APMIXED_ARMCA15PLL 1 165c1e81a3bSJames Liao #define CLK_APMIXED_ARMCA7PLL 2 166c1e81a3bSJames Liao #define CLK_APMIXED_MAINPLL 3 167c1e81a3bSJames Liao #define CLK_APMIXED_UNIVPLL 4 168c1e81a3bSJames Liao #define CLK_APMIXED_MMPLL 5 169c1e81a3bSJames Liao #define CLK_APMIXED_MSDCPLL 6 170c1e81a3bSJames Liao #define CLK_APMIXED_VENCPLL 7 171c1e81a3bSJames Liao #define CLK_APMIXED_TVDPLL 8 172c1e81a3bSJames Liao #define CLK_APMIXED_MPLL 9 173c1e81a3bSJames Liao #define CLK_APMIXED_VCODECPLL 10 174c1e81a3bSJames Liao #define CLK_APMIXED_APLL1 11 175c1e81a3bSJames Liao #define CLK_APMIXED_APLL2 12 176c1e81a3bSJames Liao #define CLK_APMIXED_LVDSPLL 13 177c1e81a3bSJames Liao #define CLK_APMIXED_MSDCPLL2 14 178c1e81a3bSJames Liao #define CLK_APMIXED_NR_CLK 15 179c1e81a3bSJames Liao 180c1e81a3bSJames Liao /* INFRA_SYS */ 181c1e81a3bSJames Liao 182c1e81a3bSJames Liao #define CLK_INFRA_DBGCLK 1 183c1e81a3bSJames Liao #define CLK_INFRA_SMI 2 184c1e81a3bSJames Liao #define CLK_INFRA_AUDIO 3 185c1e81a3bSJames Liao #define CLK_INFRA_GCE 4 186c1e81a3bSJames Liao #define CLK_INFRA_L2C_SRAM 5 187c1e81a3bSJames Liao #define CLK_INFRA_M4U 6 188c1e81a3bSJames Liao #define CLK_INFRA_CPUM 7 189c1e81a3bSJames Liao #define CLK_INFRA_KP 8 190c1e81a3bSJames Liao #define CLK_INFRA_CEC 9 191c1e81a3bSJames Liao #define CLK_INFRA_PMICSPI 10 192c1e81a3bSJames Liao #define CLK_INFRA_PMICWRAP 11 1932d61fe0fSJoe.C #define CLK_INFRA_CLK_13M 12 1942d61fe0fSJoe.C #define CLK_INFRA_NR_CLK 13 195c1e81a3bSJames Liao 196c1e81a3bSJames Liao /* PERI_SYS */ 197c1e81a3bSJames Liao 198c1e81a3bSJames Liao #define CLK_PERI_NFI 1 199c1e81a3bSJames Liao #define CLK_PERI_THERM 2 200c1e81a3bSJames Liao #define CLK_PERI_PWM1 3 201c1e81a3bSJames Liao #define CLK_PERI_PWM2 4 202c1e81a3bSJames Liao #define CLK_PERI_PWM3 5 203c1e81a3bSJames Liao #define CLK_PERI_PWM4 6 204c1e81a3bSJames Liao #define CLK_PERI_PWM5 7 205c1e81a3bSJames Liao #define CLK_PERI_PWM6 8 206c1e81a3bSJames Liao #define CLK_PERI_PWM7 9 207c1e81a3bSJames Liao #define CLK_PERI_PWM 10 208c1e81a3bSJames Liao #define CLK_PERI_USB0 11 209c1e81a3bSJames Liao #define CLK_PERI_USB1 12 210c1e81a3bSJames Liao #define CLK_PERI_AP_DMA 13 211c1e81a3bSJames Liao #define CLK_PERI_MSDC30_0 14 212c1e81a3bSJames Liao #define CLK_PERI_MSDC30_1 15 213c1e81a3bSJames Liao #define CLK_PERI_MSDC30_2 16 214c1e81a3bSJames Liao #define CLK_PERI_MSDC30_3 17 215c1e81a3bSJames Liao #define CLK_PERI_NLI_ARB 18 216c1e81a3bSJames Liao #define CLK_PERI_IRDA 19 217c1e81a3bSJames Liao #define CLK_PERI_UART0 20 218c1e81a3bSJames Liao #define CLK_PERI_UART1 21 219c1e81a3bSJames Liao #define CLK_PERI_UART2 22 220c1e81a3bSJames Liao #define CLK_PERI_UART3 23 221c1e81a3bSJames Liao #define CLK_PERI_I2C0 24 222c1e81a3bSJames Liao #define CLK_PERI_I2C1 25 223c1e81a3bSJames Liao #define CLK_PERI_I2C2 26 224c1e81a3bSJames Liao #define CLK_PERI_I2C3 27 225c1e81a3bSJames Liao #define CLK_PERI_I2C4 28 226c1e81a3bSJames Liao #define CLK_PERI_AUXADC 29 227c1e81a3bSJames Liao #define CLK_PERI_SPI0 30 228c1e81a3bSJames Liao #define CLK_PERI_I2C5 31 229c1e81a3bSJames Liao #define CLK_PERI_NFIECC 32 230c1e81a3bSJames Liao #define CLK_PERI_SPI 33 231c1e81a3bSJames Liao #define CLK_PERI_IRRX 34 232c1e81a3bSJames Liao #define CLK_PERI_I2C6 35 233c1e81a3bSJames Liao #define CLK_PERI_UART0_SEL 36 234c1e81a3bSJames Liao #define CLK_PERI_UART1_SEL 37 235c1e81a3bSJames Liao #define CLK_PERI_UART2_SEL 38 236c1e81a3bSJames Liao #define CLK_PERI_UART3_SEL 39 237c1e81a3bSJames Liao #define CLK_PERI_NR_CLK 40 238c1e81a3bSJames Liao 23929859d93SJames Liao /* IMG_SYS */ 24029859d93SJames Liao 24129859d93SJames Liao #define CLK_IMG_LARB2_SMI 1 24229859d93SJames Liao #define CLK_IMG_CAM_SMI 2 24329859d93SJames Liao #define CLK_IMG_CAM_CAM 3 24429859d93SJames Liao #define CLK_IMG_SEN_TG 4 24529859d93SJames Liao #define CLK_IMG_SEN_CAM 5 24629859d93SJames Liao #define CLK_IMG_CAM_SV 6 24729859d93SJames Liao #define CLK_IMG_FD 7 24829859d93SJames Liao #define CLK_IMG_NR_CLK 8 24929859d93SJames Liao 25029859d93SJames Liao /* MM_SYS */ 25129859d93SJames Liao 25229859d93SJames Liao #define CLK_MM_SMI_COMMON 1 25329859d93SJames Liao #define CLK_MM_SMI_LARB0 2 25429859d93SJames Liao #define CLK_MM_CAM_MDP 3 25529859d93SJames Liao #define CLK_MM_MDP_RDMA0 4 25629859d93SJames Liao #define CLK_MM_MDP_RDMA1 5 25729859d93SJames Liao #define CLK_MM_MDP_RSZ0 6 25829859d93SJames Liao #define CLK_MM_MDP_RSZ1 7 25929859d93SJames Liao #define CLK_MM_MDP_RSZ2 8 26029859d93SJames Liao #define CLK_MM_MDP_TDSHP0 9 26129859d93SJames Liao #define CLK_MM_MDP_TDSHP1 10 26229859d93SJames Liao #define CLK_MM_MDP_WDMA 11 26329859d93SJames Liao #define CLK_MM_MDP_WROT0 12 26429859d93SJames Liao #define CLK_MM_MDP_WROT1 13 26529859d93SJames Liao #define CLK_MM_FAKE_ENG 14 26629859d93SJames Liao #define CLK_MM_MUTEX_32K 15 26729859d93SJames Liao #define CLK_MM_DISP_OVL0 16 26829859d93SJames Liao #define CLK_MM_DISP_OVL1 17 26929859d93SJames Liao #define CLK_MM_DISP_RDMA0 18 27029859d93SJames Liao #define CLK_MM_DISP_RDMA1 19 27129859d93SJames Liao #define CLK_MM_DISP_RDMA2 20 27229859d93SJames Liao #define CLK_MM_DISP_WDMA0 21 27329859d93SJames Liao #define CLK_MM_DISP_WDMA1 22 27429859d93SJames Liao #define CLK_MM_DISP_COLOR0 23 27529859d93SJames Liao #define CLK_MM_DISP_COLOR1 24 27629859d93SJames Liao #define CLK_MM_DISP_AAL 25 27729859d93SJames Liao #define CLK_MM_DISP_GAMMA 26 27829859d93SJames Liao #define CLK_MM_DISP_UFOE 27 27929859d93SJames Liao #define CLK_MM_DISP_SPLIT0 28 28029859d93SJames Liao #define CLK_MM_DISP_SPLIT1 29 28129859d93SJames Liao #define CLK_MM_DISP_MERGE 30 28229859d93SJames Liao #define CLK_MM_DISP_OD 31 28329859d93SJames Liao #define CLK_MM_DISP_PWM0MM 32 28429859d93SJames Liao #define CLK_MM_DISP_PWM026M 33 28529859d93SJames Liao #define CLK_MM_DISP_PWM1MM 34 28629859d93SJames Liao #define CLK_MM_DISP_PWM126M 35 28729859d93SJames Liao #define CLK_MM_DSI0_ENGINE 36 28829859d93SJames Liao #define CLK_MM_DSI0_DIGITAL 37 28929859d93SJames Liao #define CLK_MM_DSI1_ENGINE 38 29029859d93SJames Liao #define CLK_MM_DSI1_DIGITAL 39 29129859d93SJames Liao #define CLK_MM_DPI_PIXEL 40 29229859d93SJames Liao #define CLK_MM_DPI_ENGINE 41 29329859d93SJames Liao #define CLK_MM_DPI1_PIXEL 42 29429859d93SJames Liao #define CLK_MM_DPI1_ENGINE 43 29529859d93SJames Liao #define CLK_MM_HDMI_PIXEL 44 29629859d93SJames Liao #define CLK_MM_HDMI_PLLCK 45 29729859d93SJames Liao #define CLK_MM_HDMI_AUDIO 46 29829859d93SJames Liao #define CLK_MM_HDMI_SPDIF 47 29929859d93SJames Liao #define CLK_MM_LVDS_PIXEL 48 30029859d93SJames Liao #define CLK_MM_LVDS_CTS 49 30129859d93SJames Liao #define CLK_MM_SMI_LARB4 50 30229859d93SJames Liao #define CLK_MM_HDMI_HDCP 51 30329859d93SJames Liao #define CLK_MM_HDMI_HDCP24M 52 30429859d93SJames Liao #define CLK_MM_NR_CLK 53 30529859d93SJames Liao 30629859d93SJames Liao /* VDEC_SYS */ 30729859d93SJames Liao 30829859d93SJames Liao #define CLK_VDEC_CKEN 1 30929859d93SJames Liao #define CLK_VDEC_LARB_CKEN 2 31029859d93SJames Liao #define CLK_VDEC_NR_CLK 3 31129859d93SJames Liao 31229859d93SJames Liao /* VENC_SYS */ 31329859d93SJames Liao 31429859d93SJames Liao #define CLK_VENC_CKE0 1 31529859d93SJames Liao #define CLK_VENC_CKE1 2 31629859d93SJames Liao #define CLK_VENC_CKE2 3 31729859d93SJames Liao #define CLK_VENC_CKE3 4 31829859d93SJames Liao #define CLK_VENC_NR_CLK 5 31929859d93SJames Liao 32029859d93SJames Liao /* VENCLT_SYS */ 32129859d93SJames Liao 32229859d93SJames Liao #define CLK_VENCLT_CKE0 1 32329859d93SJames Liao #define CLK_VENCLT_CKE1 2 32429859d93SJames Liao #define CLK_VENCLT_NR_CLK 3 32529859d93SJames Liao 326c1e81a3bSJames Liao #endif /* _DT_BINDINGS_CLK_MT8173_H */ 327