1a8aede79SJames Liao /* 2a8aede79SJames Liao * Copyright (c) 2014 MediaTek Inc. 3a8aede79SJames Liao * Author: James Liao <jamesjj.liao@mediatek.com> 4a8aede79SJames Liao * 5a8aede79SJames Liao * This program is free software; you can redistribute it and/or modify 6a8aede79SJames Liao * it under the terms of the GNU General Public License version 2 as 7a8aede79SJames Liao * published by the Free Software Foundation. 8a8aede79SJames Liao * 9a8aede79SJames Liao * This program is distributed in the hope that it will be useful, 10a8aede79SJames Liao * but WITHOUT ANY WARRANTY; without even the implied warranty of 11a8aede79SJames Liao * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12a8aede79SJames Liao * GNU General Public License for more details. 13a8aede79SJames Liao */ 14a8aede79SJames Liao 15a8aede79SJames Liao #ifndef _DT_BINDINGS_CLK_MT8135_H 16a8aede79SJames Liao #define _DT_BINDINGS_CLK_MT8135_H 17a8aede79SJames Liao 18a8aede79SJames Liao /* TOPCKGEN */ 19a8aede79SJames Liao 20a8aede79SJames Liao #define CLK_TOP_DSI0_LNTC_DSICLK 1 21a8aede79SJames Liao #define CLK_TOP_HDMITX_CLKDIG_CTS 2 22a8aede79SJames Liao #define CLK_TOP_CLKPH_MCK 3 23a8aede79SJames Liao #define CLK_TOP_CPUM_TCK_IN 4 24a8aede79SJames Liao #define CLK_TOP_MAINPLL_806M 5 25a8aede79SJames Liao #define CLK_TOP_MAINPLL_537P3M 6 26a8aede79SJames Liao #define CLK_TOP_MAINPLL_322P4M 7 27a8aede79SJames Liao #define CLK_TOP_MAINPLL_230P3M 8 28a8aede79SJames Liao #define CLK_TOP_UNIVPLL_624M 9 29a8aede79SJames Liao #define CLK_TOP_UNIVPLL_416M 10 30a8aede79SJames Liao #define CLK_TOP_UNIVPLL_249P6M 11 31a8aede79SJames Liao #define CLK_TOP_UNIVPLL_178P3M 12 32a8aede79SJames Liao #define CLK_TOP_UNIVPLL_48M 13 33a8aede79SJames Liao #define CLK_TOP_MMPLL_D2 14 34a8aede79SJames Liao #define CLK_TOP_MMPLL_D3 15 35a8aede79SJames Liao #define CLK_TOP_MMPLL_D5 16 36a8aede79SJames Liao #define CLK_TOP_MMPLL_D7 17 37a8aede79SJames Liao #define CLK_TOP_MMPLL_D4 18 38a8aede79SJames Liao #define CLK_TOP_MMPLL_D6 19 39a8aede79SJames Liao #define CLK_TOP_SYSPLL_D2 20 40a8aede79SJames Liao #define CLK_TOP_SYSPLL_D4 21 41a8aede79SJames Liao #define CLK_TOP_SYSPLL_D6 22 42a8aede79SJames Liao #define CLK_TOP_SYSPLL_D8 23 43a8aede79SJames Liao #define CLK_TOP_SYSPLL_D10 24 44a8aede79SJames Liao #define CLK_TOP_SYSPLL_D12 25 45a8aede79SJames Liao #define CLK_TOP_SYSPLL_D16 26 46a8aede79SJames Liao #define CLK_TOP_SYSPLL_D24 27 47a8aede79SJames Liao #define CLK_TOP_SYSPLL_D3 28 48a8aede79SJames Liao #define CLK_TOP_SYSPLL_D2P5 29 49a8aede79SJames Liao #define CLK_TOP_SYSPLL_D5 30 50a8aede79SJames Liao #define CLK_TOP_SYSPLL_D3P5 31 51a8aede79SJames Liao #define CLK_TOP_UNIVPLL1_D2 32 52a8aede79SJames Liao #define CLK_TOP_UNIVPLL1_D4 33 53a8aede79SJames Liao #define CLK_TOP_UNIVPLL1_D6 34 54a8aede79SJames Liao #define CLK_TOP_UNIVPLL1_D8 35 55a8aede79SJames Liao #define CLK_TOP_UNIVPLL1_D10 36 56a8aede79SJames Liao #define CLK_TOP_UNIVPLL2_D2 37 57a8aede79SJames Liao #define CLK_TOP_UNIVPLL2_D4 38 58a8aede79SJames Liao #define CLK_TOP_UNIVPLL2_D6 39 59a8aede79SJames Liao #define CLK_TOP_UNIVPLL2_D8 40 60a8aede79SJames Liao #define CLK_TOP_UNIVPLL_D3 41 61a8aede79SJames Liao #define CLK_TOP_UNIVPLL_D5 42 62a8aede79SJames Liao #define CLK_TOP_UNIVPLL_D7 43 63a8aede79SJames Liao #define CLK_TOP_UNIVPLL_D10 44 64a8aede79SJames Liao #define CLK_TOP_UNIVPLL_D26 45 65a8aede79SJames Liao #define CLK_TOP_APLL 46 66a8aede79SJames Liao #define CLK_TOP_APLL_D4 47 67a8aede79SJames Liao #define CLK_TOP_APLL_D8 48 68a8aede79SJames Liao #define CLK_TOP_APLL_D16 49 69a8aede79SJames Liao #define CLK_TOP_APLL_D24 50 70a8aede79SJames Liao #define CLK_TOP_LVDSPLL_D2 51 71a8aede79SJames Liao #define CLK_TOP_LVDSPLL_D4 52 72a8aede79SJames Liao #define CLK_TOP_LVDSPLL_D8 53 73a8aede79SJames Liao #define CLK_TOP_LVDSTX_CLKDIG_CT 54 74a8aede79SJames Liao #define CLK_TOP_VPLL_DPIX 55 75a8aede79SJames Liao #define CLK_TOP_TVHDMI_H 56 76a8aede79SJames Liao #define CLK_TOP_HDMITX_CLKDIG_D2 57 77a8aede79SJames Liao #define CLK_TOP_HDMITX_CLKDIG_D3 58 78a8aede79SJames Liao #define CLK_TOP_TVHDMI_D2 59 79a8aede79SJames Liao #define CLK_TOP_TVHDMI_D4 60 80a8aede79SJames Liao #define CLK_TOP_MEMPLL_MCK_D4 61 81a8aede79SJames Liao #define CLK_TOP_AXI_SEL 62 82a8aede79SJames Liao #define CLK_TOP_SMI_SEL 63 83a8aede79SJames Liao #define CLK_TOP_MFG_SEL 64 84a8aede79SJames Liao #define CLK_TOP_IRDA_SEL 65 85a8aede79SJames Liao #define CLK_TOP_CAM_SEL 66 86a8aede79SJames Liao #define CLK_TOP_AUD_INTBUS_SEL 67 87a8aede79SJames Liao #define CLK_TOP_JPG_SEL 68 88a8aede79SJames Liao #define CLK_TOP_DISP_SEL 69 89a8aede79SJames Liao #define CLK_TOP_MSDC30_1_SEL 70 90a8aede79SJames Liao #define CLK_TOP_MSDC30_2_SEL 71 91a8aede79SJames Liao #define CLK_TOP_MSDC30_3_SEL 72 92a8aede79SJames Liao #define CLK_TOP_MSDC30_4_SEL 73 93a8aede79SJames Liao #define CLK_TOP_USB20_SEL 74 94a8aede79SJames Liao #define CLK_TOP_VENC_SEL 75 95a8aede79SJames Liao #define CLK_TOP_SPI_SEL 76 96a8aede79SJames Liao #define CLK_TOP_UART_SEL 77 97a8aede79SJames Liao #define CLK_TOP_MEM_SEL 78 98a8aede79SJames Liao #define CLK_TOP_CAMTG_SEL 79 99a8aede79SJames Liao #define CLK_TOP_AUDIO_SEL 80 100a8aede79SJames Liao #define CLK_TOP_FIX_SEL 81 101a8aede79SJames Liao #define CLK_TOP_VDEC_SEL 82 102a8aede79SJames Liao #define CLK_TOP_DDRPHYCFG_SEL 83 103a8aede79SJames Liao #define CLK_TOP_DPILVDS_SEL 84 104a8aede79SJames Liao #define CLK_TOP_PMICSPI_SEL 85 105a8aede79SJames Liao #define CLK_TOP_MSDC30_0_SEL 86 106a8aede79SJames Liao #define CLK_TOP_SMI_MFG_AS_SEL 87 107a8aede79SJames Liao #define CLK_TOP_GCPU_SEL 88 108a8aede79SJames Liao #define CLK_TOP_DPI1_SEL 89 109a8aede79SJames Liao #define CLK_TOP_CCI_SEL 90 110a8aede79SJames Liao #define CLK_TOP_APLL_SEL 91 111a8aede79SJames Liao #define CLK_TOP_HDMIPLL_SEL 92 112a8aede79SJames Liao #define CLK_TOP_NR_CLK 93 113a8aede79SJames Liao 114a8aede79SJames Liao /* APMIXED_SYS */ 115a8aede79SJames Liao 116a8aede79SJames Liao #define CLK_APMIXED_ARMPLL1 1 117a8aede79SJames Liao #define CLK_APMIXED_ARMPLL2 2 118a8aede79SJames Liao #define CLK_APMIXED_MAINPLL 3 119a8aede79SJames Liao #define CLK_APMIXED_UNIVPLL 4 120a8aede79SJames Liao #define CLK_APMIXED_MMPLL 5 121a8aede79SJames Liao #define CLK_APMIXED_MSDCPLL 6 122a8aede79SJames Liao #define CLK_APMIXED_TVDPLL 7 123a8aede79SJames Liao #define CLK_APMIXED_LVDSPLL 8 124a8aede79SJames Liao #define CLK_APMIXED_AUDPLL 9 125a8aede79SJames Liao #define CLK_APMIXED_VDECPLL 10 126a8aede79SJames Liao #define CLK_APMIXED_NR_CLK 11 127a8aede79SJames Liao 128a8aede79SJames Liao /* INFRA_SYS */ 129a8aede79SJames Liao 130a8aede79SJames Liao #define CLK_INFRA_PMIC_WRAP 1 131a8aede79SJames Liao #define CLK_INFRA_PMICSPI 2 132a8aede79SJames Liao #define CLK_INFRA_CCIF1_AP_CTRL 3 133a8aede79SJames Liao #define CLK_INFRA_CCIF0_AP_CTRL 4 134a8aede79SJames Liao #define CLK_INFRA_KP 5 135a8aede79SJames Liao #define CLK_INFRA_CPUM 6 136a8aede79SJames Liao #define CLK_INFRA_M4U 7 137a8aede79SJames Liao #define CLK_INFRA_MFGAXI 8 138a8aede79SJames Liao #define CLK_INFRA_DEVAPC 9 139a8aede79SJames Liao #define CLK_INFRA_AUDIO 10 140a8aede79SJames Liao #define CLK_INFRA_MFG_BUS 11 141a8aede79SJames Liao #define CLK_INFRA_SMI 12 142a8aede79SJames Liao #define CLK_INFRA_DBGCLK 13 143a8aede79SJames Liao #define CLK_INFRA_NR_CLK 14 144a8aede79SJames Liao 145a8aede79SJames Liao /* PERI_SYS */ 146a8aede79SJames Liao 147a8aede79SJames Liao #define CLK_PERI_I2C5 1 148a8aede79SJames Liao #define CLK_PERI_I2C4 2 149a8aede79SJames Liao #define CLK_PERI_I2C3 3 150a8aede79SJames Liao #define CLK_PERI_I2C2 4 151a8aede79SJames Liao #define CLK_PERI_I2C1 5 152a8aede79SJames Liao #define CLK_PERI_I2C0 6 153a8aede79SJames Liao #define CLK_PERI_UART3 7 154a8aede79SJames Liao #define CLK_PERI_UART2 8 155a8aede79SJames Liao #define CLK_PERI_UART1 9 156a8aede79SJames Liao #define CLK_PERI_UART0 10 157a8aede79SJames Liao #define CLK_PERI_IRDA 11 158a8aede79SJames Liao #define CLK_PERI_NLI 12 159a8aede79SJames Liao #define CLK_PERI_MD_HIF 13 160a8aede79SJames Liao #define CLK_PERI_AP_HIF 14 161a8aede79SJames Liao #define CLK_PERI_MSDC30_3 15 162a8aede79SJames Liao #define CLK_PERI_MSDC30_2 16 163a8aede79SJames Liao #define CLK_PERI_MSDC30_1 17 164a8aede79SJames Liao #define CLK_PERI_MSDC20_2 18 165a8aede79SJames Liao #define CLK_PERI_MSDC20_1 19 166a8aede79SJames Liao #define CLK_PERI_AP_DMA 20 167a8aede79SJames Liao #define CLK_PERI_USB1 21 168a8aede79SJames Liao #define CLK_PERI_USB0 22 169a8aede79SJames Liao #define CLK_PERI_PWM 23 170a8aede79SJames Liao #define CLK_PERI_PWM7 24 171a8aede79SJames Liao #define CLK_PERI_PWM6 25 172a8aede79SJames Liao #define CLK_PERI_PWM5 26 173a8aede79SJames Liao #define CLK_PERI_PWM4 27 174a8aede79SJames Liao #define CLK_PERI_PWM3 28 175a8aede79SJames Liao #define CLK_PERI_PWM2 29 176a8aede79SJames Liao #define CLK_PERI_PWM1 30 177a8aede79SJames Liao #define CLK_PERI_THERM 31 178a8aede79SJames Liao #define CLK_PERI_NFI 32 179a8aede79SJames Liao #define CLK_PERI_USBSLV 33 180a8aede79SJames Liao #define CLK_PERI_USB1_MCU 34 181a8aede79SJames Liao #define CLK_PERI_USB0_MCU 35 182a8aede79SJames Liao #define CLK_PERI_GCPU 36 183a8aede79SJames Liao #define CLK_PERI_FHCTL 37 184a8aede79SJames Liao #define CLK_PERI_SPI1 38 185a8aede79SJames Liao #define CLK_PERI_AUXADC 39 186a8aede79SJames Liao #define CLK_PERI_PERI_PWRAP 40 187a8aede79SJames Liao #define CLK_PERI_I2C6 41 188a8aede79SJames Liao #define CLK_PERI_UART0_SEL 42 189a8aede79SJames Liao #define CLK_PERI_UART1_SEL 43 190a8aede79SJames Liao #define CLK_PERI_UART2_SEL 44 191a8aede79SJames Liao #define CLK_PERI_UART3_SEL 45 192a8aede79SJames Liao #define CLK_PERI_NR_CLK 46 193a8aede79SJames Liao 194a8aede79SJames Liao #endif /* _DT_BINDINGS_CLK_MT8135_H */ 195