1bda921faSChen Zhong /* 2bda921faSChen Zhong * Copyright (c) 2017 MediaTek Inc. 3bda921faSChen Zhong * Author: Chen Zhong <chen.zhong@mediatek.com> 4bda921faSChen Zhong * 5bda921faSChen Zhong * This program is free software; you can redistribute it and/or modify 6bda921faSChen Zhong * it under the terms of the GNU General Public License version 2 as 7bda921faSChen Zhong * published by the Free Software Foundation. 8bda921faSChen Zhong * 9bda921faSChen Zhong * This program is distributed in the hope that it will be useful, 10bda921faSChen Zhong * but WITHOUT ANY WARRANTY; without even the implied warranty of 11bda921faSChen Zhong * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12bda921faSChen Zhong * GNU General Public License for more details. 13bda921faSChen Zhong */ 14bda921faSChen Zhong 15bda921faSChen Zhong #ifndef _DT_BINDINGS_CLK_MT7622_H 16bda921faSChen Zhong #define _DT_BINDINGS_CLK_MT7622_H 17bda921faSChen Zhong 18bda921faSChen Zhong /* TOPCKGEN */ 19bda921faSChen Zhong 20bda921faSChen Zhong #define CLK_TOP_TO_U2_PHY 0 21bda921faSChen Zhong #define CLK_TOP_TO_U2_PHY_1P 1 22bda921faSChen Zhong #define CLK_TOP_PCIE0_PIPE_EN 2 23bda921faSChen Zhong #define CLK_TOP_PCIE1_PIPE_EN 3 24bda921faSChen Zhong #define CLK_TOP_SSUSB_TX250M 4 25bda921faSChen Zhong #define CLK_TOP_SSUSB_EQ_RX250M 5 26bda921faSChen Zhong #define CLK_TOP_SSUSB_CDR_REF 6 27bda921faSChen Zhong #define CLK_TOP_SSUSB_CDR_FB 7 28bda921faSChen Zhong #define CLK_TOP_SATA_ASIC 8 29bda921faSChen Zhong #define CLK_TOP_SATA_RBC 9 30bda921faSChen Zhong #define CLK_TOP_TO_USB3_SYS 10 31bda921faSChen Zhong #define CLK_TOP_P1_1MHZ 11 32bda921faSChen Zhong #define CLK_TOP_4MHZ 12 33bda921faSChen Zhong #define CLK_TOP_P0_1MHZ 13 34bda921faSChen Zhong #define CLK_TOP_TXCLK_SRC_PRE 14 35bda921faSChen Zhong #define CLK_TOP_RTC 15 36bda921faSChen Zhong #define CLK_TOP_MEMPLL 16 37bda921faSChen Zhong #define CLK_TOP_DMPLL 17 38bda921faSChen Zhong #define CLK_TOP_SYSPLL_D2 18 39bda921faSChen Zhong #define CLK_TOP_SYSPLL1_D2 19 40bda921faSChen Zhong #define CLK_TOP_SYSPLL1_D4 20 41bda921faSChen Zhong #define CLK_TOP_SYSPLL1_D8 21 42bda921faSChen Zhong #define CLK_TOP_SYSPLL2_D4 22 43bda921faSChen Zhong #define CLK_TOP_SYSPLL2_D8 23 44bda921faSChen Zhong #define CLK_TOP_SYSPLL_D5 24 45bda921faSChen Zhong #define CLK_TOP_SYSPLL3_D2 25 46bda921faSChen Zhong #define CLK_TOP_SYSPLL3_D4 26 47bda921faSChen Zhong #define CLK_TOP_SYSPLL4_D2 27 48bda921faSChen Zhong #define CLK_TOP_SYSPLL4_D4 28 49bda921faSChen Zhong #define CLK_TOP_SYSPLL4_D16 29 50bda921faSChen Zhong #define CLK_TOP_UNIVPLL 30 51bda921faSChen Zhong #define CLK_TOP_UNIVPLL_D2 31 52bda921faSChen Zhong #define CLK_TOP_UNIVPLL1_D2 32 53bda921faSChen Zhong #define CLK_TOP_UNIVPLL1_D4 33 54bda921faSChen Zhong #define CLK_TOP_UNIVPLL1_D8 34 55bda921faSChen Zhong #define CLK_TOP_UNIVPLL1_D16 35 56bda921faSChen Zhong #define CLK_TOP_UNIVPLL2_D2 36 57bda921faSChen Zhong #define CLK_TOP_UNIVPLL2_D4 37 58bda921faSChen Zhong #define CLK_TOP_UNIVPLL2_D8 38 59bda921faSChen Zhong #define CLK_TOP_UNIVPLL2_D16 39 60bda921faSChen Zhong #define CLK_TOP_UNIVPLL_D5 40 61bda921faSChen Zhong #define CLK_TOP_UNIVPLL3_D2 41 62bda921faSChen Zhong #define CLK_TOP_UNIVPLL3_D4 42 63bda921faSChen Zhong #define CLK_TOP_UNIVPLL3_D16 43 64bda921faSChen Zhong #define CLK_TOP_UNIVPLL_D7 44 65bda921faSChen Zhong #define CLK_TOP_UNIVPLL_D80_D4 45 66bda921faSChen Zhong #define CLK_TOP_UNIV48M 46 67bda921faSChen Zhong #define CLK_TOP_SGMIIPLL 47 68bda921faSChen Zhong #define CLK_TOP_SGMIIPLL_D2 48 69bda921faSChen Zhong #define CLK_TOP_AUD1PLL 49 70bda921faSChen Zhong #define CLK_TOP_AUD2PLL 50 71bda921faSChen Zhong #define CLK_TOP_AUD_I2S2_MCK 51 72bda921faSChen Zhong #define CLK_TOP_TO_USB3_REF 52 73bda921faSChen Zhong #define CLK_TOP_PCIE1_MAC_EN 53 74bda921faSChen Zhong #define CLK_TOP_PCIE0_MAC_EN 54 75bda921faSChen Zhong #define CLK_TOP_ETH_500M 55 76bda921faSChen Zhong #define CLK_TOP_AXI_SEL 56 77bda921faSChen Zhong #define CLK_TOP_MEM_SEL 57 78bda921faSChen Zhong #define CLK_TOP_DDRPHYCFG_SEL 58 79bda921faSChen Zhong #define CLK_TOP_ETH_SEL 59 80bda921faSChen Zhong #define CLK_TOP_PWM_SEL 60 81bda921faSChen Zhong #define CLK_TOP_F10M_REF_SEL 61 82bda921faSChen Zhong #define CLK_TOP_NFI_INFRA_SEL 62 83bda921faSChen Zhong #define CLK_TOP_FLASH_SEL 63 84bda921faSChen Zhong #define CLK_TOP_UART_SEL 64 85bda921faSChen Zhong #define CLK_TOP_SPI0_SEL 65 86bda921faSChen Zhong #define CLK_TOP_SPI1_SEL 66 87bda921faSChen Zhong #define CLK_TOP_MSDC50_0_SEL 67 88bda921faSChen Zhong #define CLK_TOP_MSDC30_0_SEL 68 89bda921faSChen Zhong #define CLK_TOP_MSDC30_1_SEL 69 90bda921faSChen Zhong #define CLK_TOP_A1SYS_HP_SEL 70 91bda921faSChen Zhong #define CLK_TOP_A2SYS_HP_SEL 71 92bda921faSChen Zhong #define CLK_TOP_INTDIR_SEL 72 93bda921faSChen Zhong #define CLK_TOP_AUD_INTBUS_SEL 73 94bda921faSChen Zhong #define CLK_TOP_PMICSPI_SEL 74 95bda921faSChen Zhong #define CLK_TOP_SCP_SEL 75 96bda921faSChen Zhong #define CLK_TOP_ATB_SEL 76 97bda921faSChen Zhong #define CLK_TOP_HIF_SEL 77 98bda921faSChen Zhong #define CLK_TOP_AUDIO_SEL 78 99bda921faSChen Zhong #define CLK_TOP_U2_SEL 79 100bda921faSChen Zhong #define CLK_TOP_AUD1_SEL 80 101bda921faSChen Zhong #define CLK_TOP_AUD2_SEL 81 102bda921faSChen Zhong #define CLK_TOP_IRRX_SEL 82 103bda921faSChen Zhong #define CLK_TOP_IRTX_SEL 83 104bda921faSChen Zhong #define CLK_TOP_ASM_L_SEL 84 105bda921faSChen Zhong #define CLK_TOP_ASM_M_SEL 85 106bda921faSChen Zhong #define CLK_TOP_ASM_H_SEL 86 107bda921faSChen Zhong #define CLK_TOP_APLL1_SEL 87 108bda921faSChen Zhong #define CLK_TOP_APLL2_SEL 88 109bda921faSChen Zhong #define CLK_TOP_I2S0_MCK_SEL 89 110bda921faSChen Zhong #define CLK_TOP_I2S1_MCK_SEL 90 111bda921faSChen Zhong #define CLK_TOP_I2S2_MCK_SEL 91 112bda921faSChen Zhong #define CLK_TOP_I2S3_MCK_SEL 92 113bda921faSChen Zhong #define CLK_TOP_APLL1_DIV 93 114bda921faSChen Zhong #define CLK_TOP_APLL2_DIV 94 115bda921faSChen Zhong #define CLK_TOP_I2S0_MCK_DIV 95 116bda921faSChen Zhong #define CLK_TOP_I2S1_MCK_DIV 96 117bda921faSChen Zhong #define CLK_TOP_I2S2_MCK_DIV 97 118bda921faSChen Zhong #define CLK_TOP_I2S3_MCK_DIV 98 119bda921faSChen Zhong #define CLK_TOP_A1SYS_HP_DIV 99 120bda921faSChen Zhong #define CLK_TOP_A2SYS_HP_DIV 100 121bda921faSChen Zhong #define CLK_TOP_APLL1_DIV_PD 101 122bda921faSChen Zhong #define CLK_TOP_APLL2_DIV_PD 102 123bda921faSChen Zhong #define CLK_TOP_I2S0_MCK_DIV_PD 103 124bda921faSChen Zhong #define CLK_TOP_I2S1_MCK_DIV_PD 104 125bda921faSChen Zhong #define CLK_TOP_I2S2_MCK_DIV_PD 105 126bda921faSChen Zhong #define CLK_TOP_I2S3_MCK_DIV_PD 106 127bda921faSChen Zhong #define CLK_TOP_A1SYS_HP_DIV_PD 107 128bda921faSChen Zhong #define CLK_TOP_A2SYS_HP_DIV_PD 108 129bda921faSChen Zhong #define CLK_TOP_NR_CLK 109 130bda921faSChen Zhong 131bda921faSChen Zhong /* INFRACFG */ 132bda921faSChen Zhong 133bda921faSChen Zhong #define CLK_INFRA_MUX1_SEL 0 134bda921faSChen Zhong #define CLK_INFRA_DBGCLK_PD 1 135bda921faSChen Zhong #define CLK_INFRA_AUDIO_PD 2 136bda921faSChen Zhong #define CLK_INFRA_IRRX_PD 3 137bda921faSChen Zhong #define CLK_INFRA_APXGPT_PD 4 138bda921faSChen Zhong #define CLK_INFRA_PMIC_PD 5 139bda921faSChen Zhong #define CLK_INFRA_TRNG 6 140bda921faSChen Zhong #define CLK_INFRA_NR_CLK 7 141bda921faSChen Zhong 142bda921faSChen Zhong /* PERICFG */ 143bda921faSChen Zhong 144bda921faSChen Zhong #define CLK_PERIBUS_SEL 0 145bda921faSChen Zhong #define CLK_PERI_THERM_PD 1 146bda921faSChen Zhong #define CLK_PERI_PWM1_PD 2 147bda921faSChen Zhong #define CLK_PERI_PWM2_PD 3 148bda921faSChen Zhong #define CLK_PERI_PWM3_PD 4 149bda921faSChen Zhong #define CLK_PERI_PWM4_PD 5 150bda921faSChen Zhong #define CLK_PERI_PWM5_PD 6 151bda921faSChen Zhong #define CLK_PERI_PWM6_PD 7 152bda921faSChen Zhong #define CLK_PERI_PWM7_PD 8 153bda921faSChen Zhong #define CLK_PERI_PWM_PD 9 154bda921faSChen Zhong #define CLK_PERI_AP_DMA_PD 10 155bda921faSChen Zhong #define CLK_PERI_MSDC30_0_PD 11 156bda921faSChen Zhong #define CLK_PERI_MSDC30_1_PD 12 157bda921faSChen Zhong #define CLK_PERI_UART0_PD 13 158bda921faSChen Zhong #define CLK_PERI_UART1_PD 14 159bda921faSChen Zhong #define CLK_PERI_UART2_PD 15 160bda921faSChen Zhong #define CLK_PERI_UART3_PD 16 161bda921faSChen Zhong #define CLK_PERI_UART4_PD 17 162bda921faSChen Zhong #define CLK_PERI_BTIF_PD 18 163bda921faSChen Zhong #define CLK_PERI_I2C0_PD 19 164bda921faSChen Zhong #define CLK_PERI_I2C1_PD 20 165bda921faSChen Zhong #define CLK_PERI_I2C2_PD 21 166bda921faSChen Zhong #define CLK_PERI_SPI1_PD 22 167bda921faSChen Zhong #define CLK_PERI_AUXADC_PD 23 168bda921faSChen Zhong #define CLK_PERI_SPI0_PD 24 169bda921faSChen Zhong #define CLK_PERI_SNFI_PD 25 170bda921faSChen Zhong #define CLK_PERI_NFI_PD 26 171bda921faSChen Zhong #define CLK_PERI_NFIECC_PD 27 172bda921faSChen Zhong #define CLK_PERI_FLASH_PD 28 173bda921faSChen Zhong #define CLK_PERI_IRTX_PD 29 174bda921faSChen Zhong #define CLK_PERI_NR_CLK 30 175bda921faSChen Zhong 176bda921faSChen Zhong /* APMIXEDSYS */ 177bda921faSChen Zhong 178bda921faSChen Zhong #define CLK_APMIXED_ARMPLL 0 179bda921faSChen Zhong #define CLK_APMIXED_MAINPLL 1 180bda921faSChen Zhong #define CLK_APMIXED_UNIV2PLL 2 181bda921faSChen Zhong #define CLK_APMIXED_ETH1PLL 3 182bda921faSChen Zhong #define CLK_APMIXED_ETH2PLL 4 183bda921faSChen Zhong #define CLK_APMIXED_AUD1PLL 5 184bda921faSChen Zhong #define CLK_APMIXED_AUD2PLL 6 185bda921faSChen Zhong #define CLK_APMIXED_TRGPLL 7 186bda921faSChen Zhong #define CLK_APMIXED_SGMIPLL 8 187bda921faSChen Zhong #define CLK_APMIXED_MAIN_CORE_EN 9 188bda921faSChen Zhong #define CLK_APMIXED_NR_CLK 10 189bda921faSChen Zhong 190bda921faSChen Zhong /* AUDIOSYS */ 191bda921faSChen Zhong 192bda921faSChen Zhong #define CLK_AUDIO_AFE 0 193bda921faSChen Zhong #define CLK_AUDIO_HDMI 1 194bda921faSChen Zhong #define CLK_AUDIO_SPDF 2 195bda921faSChen Zhong #define CLK_AUDIO_APLL 3 196bda921faSChen Zhong #define CLK_AUDIO_I2SIN1 4 197bda921faSChen Zhong #define CLK_AUDIO_I2SIN2 5 198bda921faSChen Zhong #define CLK_AUDIO_I2SIN3 6 199bda921faSChen Zhong #define CLK_AUDIO_I2SIN4 7 200bda921faSChen Zhong #define CLK_AUDIO_I2SO1 8 201bda921faSChen Zhong #define CLK_AUDIO_I2SO2 9 202bda921faSChen Zhong #define CLK_AUDIO_I2SO3 10 203bda921faSChen Zhong #define CLK_AUDIO_I2SO4 11 204bda921faSChen Zhong #define CLK_AUDIO_ASRCI1 12 205bda921faSChen Zhong #define CLK_AUDIO_ASRCI2 13 206bda921faSChen Zhong #define CLK_AUDIO_ASRCO1 14 207bda921faSChen Zhong #define CLK_AUDIO_ASRCO2 15 208bda921faSChen Zhong #define CLK_AUDIO_INTDIR 16 209bda921faSChen Zhong #define CLK_AUDIO_A1SYS 17 210bda921faSChen Zhong #define CLK_AUDIO_A2SYS 18 211bda921faSChen Zhong #define CLK_AUDIO_UL1 19 212bda921faSChen Zhong #define CLK_AUDIO_UL2 20 213bda921faSChen Zhong #define CLK_AUDIO_UL3 21 214bda921faSChen Zhong #define CLK_AUDIO_UL4 22 215bda921faSChen Zhong #define CLK_AUDIO_UL5 23 216bda921faSChen Zhong #define CLK_AUDIO_UL6 24 217bda921faSChen Zhong #define CLK_AUDIO_DL1 25 218bda921faSChen Zhong #define CLK_AUDIO_DL2 26 219bda921faSChen Zhong #define CLK_AUDIO_DL3 27 220bda921faSChen Zhong #define CLK_AUDIO_DL4 28 221bda921faSChen Zhong #define CLK_AUDIO_DL5 29 222bda921faSChen Zhong #define CLK_AUDIO_DL6 30 223bda921faSChen Zhong #define CLK_AUDIO_DLMCH 31 224bda921faSChen Zhong #define CLK_AUDIO_ARB1 32 225bda921faSChen Zhong #define CLK_AUDIO_AWB 33 226bda921faSChen Zhong #define CLK_AUDIO_AWB2 34 227bda921faSChen Zhong #define CLK_AUDIO_DAI 35 228bda921faSChen Zhong #define CLK_AUDIO_MOD 36 229bda921faSChen Zhong #define CLK_AUDIO_ASRCI3 37 230bda921faSChen Zhong #define CLK_AUDIO_ASRCI4 38 231bda921faSChen Zhong #define CLK_AUDIO_ASRCO3 39 232bda921faSChen Zhong #define CLK_AUDIO_ASRCO4 40 233bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC1 41 234bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC2 42 235bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC3 43 236bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC4 44 237bda921faSChen Zhong #define CLK_AUDIO_MEM_ASRC5 45 238bda921faSChen Zhong #define CLK_AUDIO_NR_CLK 46 239bda921faSChen Zhong 240bda921faSChen Zhong /* SSUSBSYS */ 241bda921faSChen Zhong 242bda921faSChen Zhong #define CLK_SSUSB_U2_PHY_1P_EN 0 243bda921faSChen Zhong #define CLK_SSUSB_U2_PHY_EN 1 244bda921faSChen Zhong #define CLK_SSUSB_REF_EN 2 245bda921faSChen Zhong #define CLK_SSUSB_SYS_EN 3 246bda921faSChen Zhong #define CLK_SSUSB_MCU_EN 4 247bda921faSChen Zhong #define CLK_SSUSB_DMA_EN 5 248bda921faSChen Zhong #define CLK_SSUSB_NR_CLK 6 249bda921faSChen Zhong 250bda921faSChen Zhong /* PCIESYS */ 251bda921faSChen Zhong 252bda921faSChen Zhong #define CLK_PCIE_P1_AUX_EN 0 253bda921faSChen Zhong #define CLK_PCIE_P1_OBFF_EN 1 254bda921faSChen Zhong #define CLK_PCIE_P1_AHB_EN 2 255bda921faSChen Zhong #define CLK_PCIE_P1_AXI_EN 3 256bda921faSChen Zhong #define CLK_PCIE_P1_MAC_EN 4 257bda921faSChen Zhong #define CLK_PCIE_P1_PIPE_EN 5 258bda921faSChen Zhong #define CLK_PCIE_P0_AUX_EN 6 259bda921faSChen Zhong #define CLK_PCIE_P0_OBFF_EN 7 260bda921faSChen Zhong #define CLK_PCIE_P0_AHB_EN 8 261bda921faSChen Zhong #define CLK_PCIE_P0_AXI_EN 9 262bda921faSChen Zhong #define CLK_PCIE_P0_MAC_EN 10 263bda921faSChen Zhong #define CLK_PCIE_P0_PIPE_EN 11 264bda921faSChen Zhong #define CLK_SATA_AHB_EN 12 265bda921faSChen Zhong #define CLK_SATA_AXI_EN 13 266bda921faSChen Zhong #define CLK_SATA_ASIC_EN 14 267bda921faSChen Zhong #define CLK_SATA_RBC_EN 15 268bda921faSChen Zhong #define CLK_SATA_PM_EN 16 269bda921faSChen Zhong #define CLK_PCIE_NR_CLK 17 270bda921faSChen Zhong 271bda921faSChen Zhong /* ETHSYS */ 272bda921faSChen Zhong 273bda921faSChen Zhong #define CLK_ETH_HSDMA_EN 0 274bda921faSChen Zhong #define CLK_ETH_ESW_EN 1 275bda921faSChen Zhong #define CLK_ETH_GP2_EN 2 276bda921faSChen Zhong #define CLK_ETH_GP1_EN 3 277bda921faSChen Zhong #define CLK_ETH_GP0_EN 4 278bda921faSChen Zhong #define CLK_ETH_NR_CLK 5 279bda921faSChen Zhong 280bda921faSChen Zhong /* SGMIISYS */ 281bda921faSChen Zhong 282bda921faSChen Zhong #define CLK_SGMII_TX250M_EN 0 283bda921faSChen Zhong #define CLK_SGMII_RX250M_EN 1 284bda921faSChen Zhong #define CLK_SGMII_CDR_REF 2 285bda921faSChen Zhong #define CLK_SGMII_CDR_FB 3 286bda921faSChen Zhong #define CLK_SGMII_NR_CLK 4 287bda921faSChen Zhong 288bda921faSChen Zhong #endif /* _DT_BINDINGS_CLK_MT7622_H */ 289bda921faSChen Zhong 290