1eb7beb65SMars Cheng /* SPDX-License-Identifier: GPL-2.0 */ 2eb7beb65SMars Cheng 3eb7beb65SMars Cheng #ifndef _DT_BINDINGS_CLK_MT6765_H 4eb7beb65SMars Cheng #define _DT_BINDINGS_CLK_MT6765_H 5eb7beb65SMars Cheng 6eb7beb65SMars Cheng /* FIX Clks */ 7eb7beb65SMars Cheng #define CLK_TOP_CLK26M 0 8eb7beb65SMars Cheng 9eb7beb65SMars Cheng /* APMIXEDSYS */ 10eb7beb65SMars Cheng #define CLK_APMIXED_ARMPLL_L 0 11eb7beb65SMars Cheng #define CLK_APMIXED_ARMPLL 1 12eb7beb65SMars Cheng #define CLK_APMIXED_CCIPLL 2 13eb7beb65SMars Cheng #define CLK_APMIXED_MAINPLL 3 14eb7beb65SMars Cheng #define CLK_APMIXED_MFGPLL 4 15eb7beb65SMars Cheng #define CLK_APMIXED_MMPLL 5 16eb7beb65SMars Cheng #define CLK_APMIXED_UNIV2PLL 6 17eb7beb65SMars Cheng #define CLK_APMIXED_MSDCPLL 7 18eb7beb65SMars Cheng #define CLK_APMIXED_APLL1 8 19eb7beb65SMars Cheng #define CLK_APMIXED_MPLL 9 20eb7beb65SMars Cheng #define CLK_APMIXED_ULPOSC1 10 21eb7beb65SMars Cheng #define CLK_APMIXED_ULPOSC2 11 22eb7beb65SMars Cheng #define CLK_APMIXED_SSUSB26M 12 23eb7beb65SMars Cheng #define CLK_APMIXED_APPLL26M 13 24eb7beb65SMars Cheng #define CLK_APMIXED_MIPIC0_26M 14 25eb7beb65SMars Cheng #define CLK_APMIXED_MDPLLGP26M 15 26eb7beb65SMars Cheng #define CLK_APMIXED_MMSYS_F26M 16 27eb7beb65SMars Cheng #define CLK_APMIXED_UFS26M 17 28eb7beb65SMars Cheng #define CLK_APMIXED_MIPIC1_26M 18 29eb7beb65SMars Cheng #define CLK_APMIXED_MEMPLL26M 19 30eb7beb65SMars Cheng #define CLK_APMIXED_CLKSQ_LVPLL_26M 20 31eb7beb65SMars Cheng #define CLK_APMIXED_MIPID0_26M 21 32eb7beb65SMars Cheng #define CLK_APMIXED_NR_CLK 22 33eb7beb65SMars Cheng 34eb7beb65SMars Cheng /* TOPCKGEN */ 35eb7beb65SMars Cheng #define CLK_TOP_SYSPLL 0 36eb7beb65SMars Cheng #define CLK_TOP_SYSPLL_D2 1 37eb7beb65SMars Cheng #define CLK_TOP_SYSPLL1_D2 2 38eb7beb65SMars Cheng #define CLK_TOP_SYSPLL1_D4 3 39eb7beb65SMars Cheng #define CLK_TOP_SYSPLL1_D8 4 40eb7beb65SMars Cheng #define CLK_TOP_SYSPLL1_D16 5 41eb7beb65SMars Cheng #define CLK_TOP_SYSPLL_D3 6 42eb7beb65SMars Cheng #define CLK_TOP_SYSPLL2_D2 7 43eb7beb65SMars Cheng #define CLK_TOP_SYSPLL2_D4 8 44eb7beb65SMars Cheng #define CLK_TOP_SYSPLL2_D8 9 45eb7beb65SMars Cheng #define CLK_TOP_SYSPLL_D5 10 46eb7beb65SMars Cheng #define CLK_TOP_SYSPLL3_D2 11 47eb7beb65SMars Cheng #define CLK_TOP_SYSPLL3_D4 12 48eb7beb65SMars Cheng #define CLK_TOP_SYSPLL_D7 13 49eb7beb65SMars Cheng #define CLK_TOP_SYSPLL4_D2 14 50eb7beb65SMars Cheng #define CLK_TOP_SYSPLL4_D4 15 51eb7beb65SMars Cheng #define CLK_TOP_USB20_192M 16 52eb7beb65SMars Cheng #define CLK_TOP_USB20_192M_D4 17 53eb7beb65SMars Cheng #define CLK_TOP_USB20_192M_D8 18 54eb7beb65SMars Cheng #define CLK_TOP_USB20_192M_D16 19 55eb7beb65SMars Cheng #define CLK_TOP_USB20_192M_D32 20 56eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL 21 57eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL_D2 22 58eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL1_D2 23 59eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL1_D4 24 60eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL_D3 25 61eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL2_D2 26 62eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL2_D4 27 63eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL2_D8 28 64eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL2_D32 29 65eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL_D5 30 66eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL3_D2 31 67eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL3_D4 32 68eb7beb65SMars Cheng #define CLK_TOP_MMPLL 33 69eb7beb65SMars Cheng #define CLK_TOP_MMPLL_D2 34 70eb7beb65SMars Cheng #define CLK_TOP_MPLL 35 71eb7beb65SMars Cheng #define CLK_TOP_DA_MPLL_104M_DIV 36 72eb7beb65SMars Cheng #define CLK_TOP_DA_MPLL_52M_DIV 37 73eb7beb65SMars Cheng #define CLK_TOP_MFGPLL 38 74eb7beb65SMars Cheng #define CLK_TOP_MSDCPLL 39 75eb7beb65SMars Cheng #define CLK_TOP_MSDCPLL_D2 40 76eb7beb65SMars Cheng #define CLK_TOP_APLL1 41 77eb7beb65SMars Cheng #define CLK_TOP_APLL1_D2 42 78eb7beb65SMars Cheng #define CLK_TOP_APLL1_D4 43 79eb7beb65SMars Cheng #define CLK_TOP_APLL1_D8 44 80eb7beb65SMars Cheng #define CLK_TOP_ULPOSC1 45 81eb7beb65SMars Cheng #define CLK_TOP_ULPOSC1_D2 46 82eb7beb65SMars Cheng #define CLK_TOP_ULPOSC1_D4 47 83eb7beb65SMars Cheng #define CLK_TOP_ULPOSC1_D8 48 84eb7beb65SMars Cheng #define CLK_TOP_ULPOSC1_D16 49 85eb7beb65SMars Cheng #define CLK_TOP_ULPOSC1_D32 50 86eb7beb65SMars Cheng #define CLK_TOP_DMPLL 51 87eb7beb65SMars Cheng #define CLK_TOP_F_FRTC 52 88eb7beb65SMars Cheng #define CLK_TOP_F_F26M 53 89eb7beb65SMars Cheng #define CLK_TOP_AXI 54 90eb7beb65SMars Cheng #define CLK_TOP_MM 55 91eb7beb65SMars Cheng #define CLK_TOP_SCP 56 92eb7beb65SMars Cheng #define CLK_TOP_MFG 57 93eb7beb65SMars Cheng #define CLK_TOP_F_FUART 58 94eb7beb65SMars Cheng #define CLK_TOP_SPI 59 95eb7beb65SMars Cheng #define CLK_TOP_MSDC50_0 60 96eb7beb65SMars Cheng #define CLK_TOP_MSDC30_1 61 97eb7beb65SMars Cheng #define CLK_TOP_AUDIO 62 98eb7beb65SMars Cheng #define CLK_TOP_AUD_1 63 99eb7beb65SMars Cheng #define CLK_TOP_AUD_ENGEN1 64 100eb7beb65SMars Cheng #define CLK_TOP_F_FDISP_PWM 65 101eb7beb65SMars Cheng #define CLK_TOP_SSPM 66 102eb7beb65SMars Cheng #define CLK_TOP_DXCC 67 103eb7beb65SMars Cheng #define CLK_TOP_I2C 68 104eb7beb65SMars Cheng #define CLK_TOP_F_FPWM 69 105eb7beb65SMars Cheng #define CLK_TOP_F_FSENINF 70 106eb7beb65SMars Cheng #define CLK_TOP_AES_FDE 71 107eb7beb65SMars Cheng #define CLK_TOP_F_BIST2FPC 72 108eb7beb65SMars Cheng #define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 109eb7beb65SMars Cheng #define CLK_TOP_ARMPLL_DIVIDER_PLL1 74 110eb7beb65SMars Cheng #define CLK_TOP_ARMPLL_DIVIDER_PLL2 75 111eb7beb65SMars Cheng #define CLK_TOP_DA_USB20_48M_DIV 76 112eb7beb65SMars Cheng #define CLK_TOP_DA_UNIV_48M_DIV 77 113eb7beb65SMars Cheng #define CLK_TOP_APLL12_DIV0 78 114eb7beb65SMars Cheng #define CLK_TOP_APLL12_DIV1 79 115eb7beb65SMars Cheng #define CLK_TOP_APLL12_DIV2 80 116eb7beb65SMars Cheng #define CLK_TOP_APLL12_DIV3 81 117eb7beb65SMars Cheng #define CLK_TOP_ARMPLL_DIVIDER_PLL0_EN 82 118eb7beb65SMars Cheng #define CLK_TOP_ARMPLL_DIVIDER_PLL1_EN 83 119eb7beb65SMars Cheng #define CLK_TOP_ARMPLL_DIVIDER_PLL2_EN 84 120eb7beb65SMars Cheng #define CLK_TOP_FMEM_OCC_DRC_EN 85 121eb7beb65SMars Cheng #define CLK_TOP_USB20_48M_EN 86 122eb7beb65SMars Cheng #define CLK_TOP_UNIVPLL_48M_EN 87 123eb7beb65SMars Cheng #define CLK_TOP_MPLL_104M_EN 88 124eb7beb65SMars Cheng #define CLK_TOP_MPLL_52M_EN 89 125eb7beb65SMars Cheng #define CLK_TOP_F_UFS_MP_SAP_CFG_EN 90 126eb7beb65SMars Cheng #define CLK_TOP_F_BIST2FPC_EN 91 127eb7beb65SMars Cheng #define CLK_TOP_MD_32K 92 128eb7beb65SMars Cheng #define CLK_TOP_MD_26M 93 129eb7beb65SMars Cheng #define CLK_TOP_MD2_32K 94 130eb7beb65SMars Cheng #define CLK_TOP_MD2_26M 95 131eb7beb65SMars Cheng #define CLK_TOP_AXI_SEL 96 132eb7beb65SMars Cheng #define CLK_TOP_MEM_SEL 97 133eb7beb65SMars Cheng #define CLK_TOP_MM_SEL 98 134eb7beb65SMars Cheng #define CLK_TOP_SCP_SEL 99 135eb7beb65SMars Cheng #define CLK_TOP_MFG_SEL 100 136eb7beb65SMars Cheng #define CLK_TOP_ATB_SEL 101 137eb7beb65SMars Cheng #define CLK_TOP_CAMTG_SEL 102 138eb7beb65SMars Cheng #define CLK_TOP_CAMTG1_SEL 103 139eb7beb65SMars Cheng #define CLK_TOP_CAMTG2_SEL 104 140eb7beb65SMars Cheng #define CLK_TOP_CAMTG3_SEL 105 141eb7beb65SMars Cheng #define CLK_TOP_UART_SEL 106 142eb7beb65SMars Cheng #define CLK_TOP_SPI_SEL 107 143eb7beb65SMars Cheng #define CLK_TOP_MSDC50_0_HCLK_SEL 108 144eb7beb65SMars Cheng #define CLK_TOP_MSDC50_0_SEL 109 145eb7beb65SMars Cheng #define CLK_TOP_MSDC30_1_SEL 110 146eb7beb65SMars Cheng #define CLK_TOP_AUDIO_SEL 111 147eb7beb65SMars Cheng #define CLK_TOP_AUD_INTBUS_SEL 112 148eb7beb65SMars Cheng #define CLK_TOP_AUD_1_SEL 113 149eb7beb65SMars Cheng #define CLK_TOP_AUD_ENGEN1_SEL 114 150eb7beb65SMars Cheng #define CLK_TOP_DISP_PWM_SEL 115 151eb7beb65SMars Cheng #define CLK_TOP_SSPM_SEL 116 152eb7beb65SMars Cheng #define CLK_TOP_DXCC_SEL 117 153eb7beb65SMars Cheng #define CLK_TOP_USB_TOP_SEL 118 154eb7beb65SMars Cheng #define CLK_TOP_SPM_SEL 119 155eb7beb65SMars Cheng #define CLK_TOP_I2C_SEL 120 156eb7beb65SMars Cheng #define CLK_TOP_PWM_SEL 121 157eb7beb65SMars Cheng #define CLK_TOP_SENINF_SEL 122 158eb7beb65SMars Cheng #define CLK_TOP_AES_FDE_SEL 123 159eb7beb65SMars Cheng #define CLK_TOP_PWRAP_ULPOSC_SEL 124 160eb7beb65SMars Cheng #define CLK_TOP_CAMTM_SEL 125 161eb7beb65SMars Cheng #define CLK_TOP_NR_CLK 126 162eb7beb65SMars Cheng 163eb7beb65SMars Cheng /* INFRACFG */ 164eb7beb65SMars Cheng #define CLK_IFR_ICUSB 0 165eb7beb65SMars Cheng #define CLK_IFR_GCE 1 166eb7beb65SMars Cheng #define CLK_IFR_THERM 2 167eb7beb65SMars Cheng #define CLK_IFR_I2C_AP 3 168eb7beb65SMars Cheng #define CLK_IFR_I2C_CCU 4 169eb7beb65SMars Cheng #define CLK_IFR_I2C_SSPM 5 170eb7beb65SMars Cheng #define CLK_IFR_I2C_RSV 6 171eb7beb65SMars Cheng #define CLK_IFR_PWM_HCLK 7 172eb7beb65SMars Cheng #define CLK_IFR_PWM1 8 173eb7beb65SMars Cheng #define CLK_IFR_PWM2 9 174eb7beb65SMars Cheng #define CLK_IFR_PWM3 10 175eb7beb65SMars Cheng #define CLK_IFR_PWM4 11 176eb7beb65SMars Cheng #define CLK_IFR_PWM5 12 177eb7beb65SMars Cheng #define CLK_IFR_PWM 13 178eb7beb65SMars Cheng #define CLK_IFR_UART0 14 179eb7beb65SMars Cheng #define CLK_IFR_UART1 15 180eb7beb65SMars Cheng #define CLK_IFR_GCE_26M 16 181eb7beb65SMars Cheng #define CLK_IFR_CQ_DMA_FPC 17 182eb7beb65SMars Cheng #define CLK_IFR_BTIF 18 183eb7beb65SMars Cheng #define CLK_IFR_SPI0 19 184eb7beb65SMars Cheng #define CLK_IFR_MSDC0 20 185eb7beb65SMars Cheng #define CLK_IFR_MSDC1 21 186eb7beb65SMars Cheng #define CLK_IFR_TRNG 22 187eb7beb65SMars Cheng #define CLK_IFR_AUXADC 23 188eb7beb65SMars Cheng #define CLK_IFR_CCIF1_AP 24 189eb7beb65SMars Cheng #define CLK_IFR_CCIF1_MD 25 190eb7beb65SMars Cheng #define CLK_IFR_AUXADC_MD 26 191eb7beb65SMars Cheng #define CLK_IFR_AP_DMA 27 192eb7beb65SMars Cheng #define CLK_IFR_DEVICE_APC 28 193eb7beb65SMars Cheng #define CLK_IFR_CCIF_AP 29 194eb7beb65SMars Cheng #define CLK_IFR_AUDIO 30 195eb7beb65SMars Cheng #define CLK_IFR_CCIF_MD 31 196eb7beb65SMars Cheng #define CLK_IFR_RG_PWM_FBCLK6 32 197eb7beb65SMars Cheng #define CLK_IFR_DISP_PWM 33 198eb7beb65SMars Cheng #define CLK_IFR_CLDMA_BCLK 34 199eb7beb65SMars Cheng #define CLK_IFR_AUDIO_26M_BCLK 35 200eb7beb65SMars Cheng #define CLK_IFR_SPI1 36 201eb7beb65SMars Cheng #define CLK_IFR_I2C4 37 202eb7beb65SMars Cheng #define CLK_IFR_SPI2 38 203eb7beb65SMars Cheng #define CLK_IFR_SPI3 39 204eb7beb65SMars Cheng #define CLK_IFR_I2C5 40 205eb7beb65SMars Cheng #define CLK_IFR_I2C5_ARBITER 41 206eb7beb65SMars Cheng #define CLK_IFR_I2C5_IMM 42 207eb7beb65SMars Cheng #define CLK_IFR_I2C1_ARBITER 43 208eb7beb65SMars Cheng #define CLK_IFR_I2C1_IMM 44 209eb7beb65SMars Cheng #define CLK_IFR_I2C2_ARBITER 45 210eb7beb65SMars Cheng #define CLK_IFR_I2C2_IMM 46 211eb7beb65SMars Cheng #define CLK_IFR_SPI4 47 212eb7beb65SMars Cheng #define CLK_IFR_SPI5 48 213eb7beb65SMars Cheng #define CLK_IFR_CQ_DMA 49 214eb7beb65SMars Cheng #define CLK_IFR_FAES_FDE 50 215eb7beb65SMars Cheng #define CLK_IFR_MSDC0_SELF 51 216eb7beb65SMars Cheng #define CLK_IFR_MSDC1_SELF 52 217eb7beb65SMars Cheng #define CLK_IFR_I2C6 53 218eb7beb65SMars Cheng #define CLK_IFR_AP_MSDC0 54 219eb7beb65SMars Cheng #define CLK_IFR_MD_MSDC0 55 220eb7beb65SMars Cheng #define CLK_IFR_MSDC0_SRC 56 221eb7beb65SMars Cheng #define CLK_IFR_MSDC1_SRC 57 222eb7beb65SMars Cheng #define CLK_IFR_AES_TOP0_BCLK 58 223eb7beb65SMars Cheng #define CLK_IFR_MCU_PM_BCLK 59 224eb7beb65SMars Cheng #define CLK_IFR_CCIF2_AP 60 225eb7beb65SMars Cheng #define CLK_IFR_CCIF2_MD 61 226eb7beb65SMars Cheng #define CLK_IFR_CCIF3_AP 62 227eb7beb65SMars Cheng #define CLK_IFR_CCIF3_MD 63 228eb7beb65SMars Cheng #define CLK_IFR_NR_CLK 64 229eb7beb65SMars Cheng 230eb7beb65SMars Cheng /* AUDIO */ 231eb7beb65SMars Cheng #define CLK_AUDIO_AFE 0 232eb7beb65SMars Cheng #define CLK_AUDIO_22M 1 233eb7beb65SMars Cheng #define CLK_AUDIO_APLL_TUNER 2 234eb7beb65SMars Cheng #define CLK_AUDIO_ADC 3 235eb7beb65SMars Cheng #define CLK_AUDIO_DAC 4 236eb7beb65SMars Cheng #define CLK_AUDIO_DAC_PREDIS 5 237eb7beb65SMars Cheng #define CLK_AUDIO_TML 6 238eb7beb65SMars Cheng #define CLK_AUDIO_I2S1_BCLK 7 239eb7beb65SMars Cheng #define CLK_AUDIO_I2S2_BCLK 8 240eb7beb65SMars Cheng #define CLK_AUDIO_I2S3_BCLK 9 241eb7beb65SMars Cheng #define CLK_AUDIO_I2S4_BCLK 10 242eb7beb65SMars Cheng #define CLK_AUDIO_NR_CLK 11 243eb7beb65SMars Cheng 244eb7beb65SMars Cheng /* MIPI_RX_ANA_CSI0A */ 245eb7beb65SMars Cheng 246eb7beb65SMars Cheng #define CLK_MIPI0A_CSR_CSI_EN_0A 0 247eb7beb65SMars Cheng #define CLK_MIPI0A_NR_CLK 1 248eb7beb65SMars Cheng 249eb7beb65SMars Cheng /* MMSYS_CONFIG */ 250eb7beb65SMars Cheng 251eb7beb65SMars Cheng #define CLK_MM_MDP_RDMA0 0 252eb7beb65SMars Cheng #define CLK_MM_MDP_CCORR0 1 253eb7beb65SMars Cheng #define CLK_MM_MDP_RSZ0 2 254eb7beb65SMars Cheng #define CLK_MM_MDP_RSZ1 3 255eb7beb65SMars Cheng #define CLK_MM_MDP_TDSHP0 4 256eb7beb65SMars Cheng #define CLK_MM_MDP_WROT0 5 257eb7beb65SMars Cheng #define CLK_MM_MDP_WDMA0 6 258eb7beb65SMars Cheng #define CLK_MM_DISP_OVL0 7 259eb7beb65SMars Cheng #define CLK_MM_DISP_OVL0_2L 8 260eb7beb65SMars Cheng #define CLK_MM_DISP_RSZ0 9 261eb7beb65SMars Cheng #define CLK_MM_DISP_RDMA0 10 262eb7beb65SMars Cheng #define CLK_MM_DISP_WDMA0 11 263eb7beb65SMars Cheng #define CLK_MM_DISP_COLOR0 12 264eb7beb65SMars Cheng #define CLK_MM_DISP_CCORR0 13 265eb7beb65SMars Cheng #define CLK_MM_DISP_AAL0 14 266eb7beb65SMars Cheng #define CLK_MM_DISP_GAMMA0 15 267eb7beb65SMars Cheng #define CLK_MM_DISP_DITHER0 16 268eb7beb65SMars Cheng #define CLK_MM_DSI0 17 269eb7beb65SMars Cheng #define CLK_MM_FAKE_ENG 18 270eb7beb65SMars Cheng #define CLK_MM_SMI_COMMON 19 271eb7beb65SMars Cheng #define CLK_MM_SMI_LARB0 20 272eb7beb65SMars Cheng #define CLK_MM_SMI_COMM0 21 273eb7beb65SMars Cheng #define CLK_MM_SMI_COMM1 22 274eb7beb65SMars Cheng #define CLK_MM_CAM_MDP 23 275eb7beb65SMars Cheng #define CLK_MM_SMI_IMG 24 276eb7beb65SMars Cheng #define CLK_MM_SMI_CAM 25 277eb7beb65SMars Cheng #define CLK_MM_IMG_DL_RELAY 26 278eb7beb65SMars Cheng #define CLK_MM_IMG_DL_ASYNC_TOP 27 279eb7beb65SMars Cheng #define CLK_MM_DIG_DSI 28 280eb7beb65SMars Cheng #define CLK_MM_F26M_HRTWT 29 281eb7beb65SMars Cheng #define CLK_MM_NR_CLK 30 282eb7beb65SMars Cheng 283eb7beb65SMars Cheng /* IMGSYS */ 284eb7beb65SMars Cheng 285eb7beb65SMars Cheng #define CLK_IMG_LARB2 0 286eb7beb65SMars Cheng #define CLK_IMG_DIP 1 287eb7beb65SMars Cheng #define CLK_IMG_FDVT 2 288eb7beb65SMars Cheng #define CLK_IMG_DPE 3 289eb7beb65SMars Cheng #define CLK_IMG_RSC 4 290eb7beb65SMars Cheng #define CLK_IMG_NR_CLK 5 291eb7beb65SMars Cheng 292eb7beb65SMars Cheng /* VENCSYS */ 293eb7beb65SMars Cheng 294eb7beb65SMars Cheng #define CLK_VENC_SET0_LARB 0 295eb7beb65SMars Cheng #define CLK_VENC_SET1_VENC 1 296eb7beb65SMars Cheng #define CLK_VENC_SET2_JPGENC 2 297eb7beb65SMars Cheng #define CLK_VENC_SET3_VDEC 3 298eb7beb65SMars Cheng #define CLK_VENC_NR_CLK 4 299eb7beb65SMars Cheng 300eb7beb65SMars Cheng /* CAMSYS */ 301eb7beb65SMars Cheng 302eb7beb65SMars Cheng #define CLK_CAM_LARB3 0 303eb7beb65SMars Cheng #define CLK_CAM_DFP_VAD 1 304eb7beb65SMars Cheng #define CLK_CAM 2 305eb7beb65SMars Cheng #define CLK_CAMTG 3 306eb7beb65SMars Cheng #define CLK_CAM_SENINF 4 307eb7beb65SMars Cheng #define CLK_CAMSV0 5 308eb7beb65SMars Cheng #define CLK_CAMSV1 6 309eb7beb65SMars Cheng #define CLK_CAMSV2 7 310eb7beb65SMars Cheng #define CLK_CAM_CCU 8 311eb7beb65SMars Cheng #define CLK_CAM_NR_CLK 9 312eb7beb65SMars Cheng 313eb7beb65SMars Cheng #endif /* _DT_BINDINGS_CLK_MT6765_H */ 314