1b7f1a721Sweiyi.lu@mediatek.com /* 2b7f1a721Sweiyi.lu@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3b7f1a721Sweiyi.lu@mediatek.com * Author: Weiyi Lu <weiyi.lu@mediatek.com> 4b7f1a721Sweiyi.lu@mediatek.com * 5b7f1a721Sweiyi.lu@mediatek.com * This program is free software; you can redistribute it and/or modify 6b7f1a721Sweiyi.lu@mediatek.com * it under the terms of the GNU General Public License version 2 as 7b7f1a721Sweiyi.lu@mediatek.com * published by the Free Software Foundation. 8b7f1a721Sweiyi.lu@mediatek.com * 9b7f1a721Sweiyi.lu@mediatek.com * This program is distributed in the hope that it will be useful, 10b7f1a721Sweiyi.lu@mediatek.com * but WITHOUT ANY WARRANTY; without even the implied warranty of 11b7f1a721Sweiyi.lu@mediatek.com * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12b7f1a721Sweiyi.lu@mediatek.com * GNU General Public License for more details. 13b7f1a721Sweiyi.lu@mediatek.com */ 14b7f1a721Sweiyi.lu@mediatek.com 15b7f1a721Sweiyi.lu@mediatek.com #ifndef _DT_BINDINGS_CLK_MT2712_H 16b7f1a721Sweiyi.lu@mediatek.com #define _DT_BINDINGS_CLK_MT2712_H 17b7f1a721Sweiyi.lu@mediatek.com 18b7f1a721Sweiyi.lu@mediatek.com /* APMIXEDSYS */ 19b7f1a721Sweiyi.lu@mediatek.com 20b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_MAINPLL 0 21b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_UNIVPLL 1 22b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_VCODECPLL 2 23b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_VENCPLL 3 24b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_APLL1 4 25b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_APLL2 5 26b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_LVDSPLL 6 27b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_LVDSPLL2 7 28b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_MSDCPLL 8 29b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_MSDCPLL2 9 30b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_TVDPLL 10 31b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_MMPLL 11 32b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_ARMCA35PLL 12 33b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_ARMCA72PLL 13 34b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_ETHERPLL 14 35b7f1a721Sweiyi.lu@mediatek.com #define CLK_APMIXED_NR_CLK 15 36b7f1a721Sweiyi.lu@mediatek.com 37b7f1a721Sweiyi.lu@mediatek.com /* TOPCKGEN */ 38b7f1a721Sweiyi.lu@mediatek.com 39b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ARMCA35PLL 0 40b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ARMCA35PLL_600M 1 41b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ARMCA35PLL_400M 2 42b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ARMCA72PLL 3 43b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL 4 44b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL_D2 5 45b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL1_D2 6 46b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL1_D4 7 47b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL1_D8 8 48b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL1_D16 9 49b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL_D3 10 50b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL2_D2 11 51b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL2_D4 12 52b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL_D5 13 53b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL3_D2 14 54b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL3_D4 15 55b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL_D7 16 56b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL4_D2 17 57b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYSPLL4_D4 18 58b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL 19 59b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL_D7 20 60b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL_D26 21 61b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL_D52 22 62b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL_D104 23 63b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL_D208 24 64b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL_D2 25 65b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL1_D2 26 66b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL1_D4 27 67b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL1_D8 28 68b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL_D3 29 69b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL2_D2 30 70b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL2_D4 31 71b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL2_D8 32 72b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL_D5 33 73b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL3_D2 34 74b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL3_D4 35 75b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UNIVPLL3_D8 36 76b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_F_MP0_PLL1 37 77b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_F_MP0_PLL2 38 78b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_F_BIG_PLL1 39 79b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_F_BIG_PLL2 40 80b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_F_BUS_PLL1 41 81b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_F_BUS_PLL2 42 82b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL1 43 83b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL1_D2 44 84b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL1_D4 45 85b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL1_D8 46 86b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL1_D16 47 87b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL2 48 88b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL2_D2 49 89b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL2_D4 50 90b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL2_D8 51 91b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL2_D16 52 92b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSPLL 53 93b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSPLL_D2 54 94b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSPLL_D4 55 95b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSPLL_D8 56 96b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSPLL2 57 97b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSPLL2_D2 58 98b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSPLL2_D4 59 99b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSPLL2_D8 60 100b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ETHERPLL_125M 61 101b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ETHERPLL_50M 62 102b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CVBS 63 103b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CVBS_D2 64 104b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SYS_26M 65 105b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MMPLL 66 106b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MMPLL_D2 67 107b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_VENCPLL 68 108b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_VENCPLL_D2 69 109b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_VCODECPLL 70 110b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_VCODECPLL_D2 71 111b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TVDPLL 72 112b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TVDPLL_D2 73 113b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TVDPLL_D4 74 114b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TVDPLL_D8 75 115b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TVDPLL_429M 76 116b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TVDPLL_429M_D2 77 117b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TVDPLL_429M_D4 78 118b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDCPLL 79 119b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDCPLL_D2 80 120b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDCPLL_D4 81 121b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDCPLL2 82 122b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDCPLL2_D2 83 123b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDCPLL2_D4 84 124b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CLK26M_D2 85 125b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_D2A_ULCLK_6P5M 86 126b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_VPLL3_DPIX 87 127b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_VPLL_DPIX 88 128b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LTEPLL_FS26M 89 129b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_DMPLL 90 130b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_DSI0_LNTC 91 131b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_DSI1_LNTC 92 132b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSTX3_CLKDIG_CTS 93 133b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_LVDSTX_CLKDIG_CTS 94 134b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CLKRTC_EXT 95 135b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CLKRTC_INT 96 136b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CSI0 97 137b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CVBSPLL 98 138b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_AXI_SEL 99 139b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MEM_SEL 100 140b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MM_SEL 101 141b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_PWM_SEL 102 142b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_VDEC_SEL 103 143b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_VENC_SEL 104 144b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MFG_SEL 105 145b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CAMTG_SEL 106 146b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_UART_SEL 107 147b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SPI_SEL 108 148b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_USB20_SEL 109 149b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_USB30_SEL 110 150b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDC50_0_HCLK_SEL 111 151b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDC50_0_SEL 112 152b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDC30_1_SEL 113 153b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDC30_2_SEL 114 154b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDC30_3_SEL 115 155b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_AUDIO_SEL 116 156b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_AUD_INTBUS_SEL 117 157b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_PMICSPI_SEL 118 158b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_DPILVDS1_SEL 119 159b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ATB_SEL 120 160b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_NR_SEL 121 161b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_NFI2X_SEL 122 162b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_IRDA_SEL 123 163b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CCI400_SEL 124 164b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_AUD_1_SEL 125 165b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_AUD_2_SEL 126 166b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MEM_MFG_IN_AS_SEL 127 167b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_AXI_MFG_IN_AS_SEL 128 168b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SCAM_SEL 129 169b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_NFIECC_SEL 130 170b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_PE2_MAC_P0_SEL 131 171b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_PE2_MAC_P1_SEL 132 172b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_DPILVDS_SEL 133 173b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDC50_3_HCLK_SEL 134 174b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_HDCP_SEL 135 175b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_HDCP_24M_SEL 136 176b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_RTC_SEL 137 177b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SPINOR_SEL 138 178b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_SEL 139 179b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL2_SEL 140 180b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_A1SYS_HP_SEL 141 181b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_A2SYS_HP_SEL 142 182b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ASM_L_SEL 143 183b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ASM_M_SEL 144 184b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ASM_H_SEL 145 185b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_I2SO1_SEL 146 186b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_I2SO2_SEL 147 187b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_I2SO3_SEL 148 188b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TDMO0_SEL 149 189b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TDMO1_SEL 150 190b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_I2SI1_SEL 151 191b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_I2SI2_SEL 152 192b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_I2SI3_SEL 153 193b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ETHER_125M_SEL 154 194b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ETHER_50M_SEL 155 195b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_JPGDEC_SEL 156 196b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_SPISLV_SEL 157 197b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_ETHER_50M_RMII_SEL 158 198b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CAM2TG_SEL 159 199b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_DI_SEL 160 200b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_TVD_SEL 161 201b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_I2C_SEL 162 202b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_PWM_INFRA_SEL 163 203b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_MSDC0P_AES_SEL 164 204b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_CMSYS_SEL 165 205b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_GCPU_SEL 166 206b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_AUD_APLL1_SEL 167 207b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_AUD_APLL2_SEL 168 208b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169 209b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV0 170 210b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV1 171 211b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV2 172 212b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV3 173 213b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV4 174 214b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV5 175 215b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV6 176 216b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV7 177 217b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV_PDN0 178 218b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV_PDN1 179 219b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV_PDN2 180 220b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV_PDN3 181 221b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV_PDN4 182 222b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV_PDN5 183 223b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV_PDN6 184 224b7f1a721Sweiyi.lu@mediatek.com #define CLK_TOP_APLL_DIV_PDN7 185 2258465baaeSWeiyi Lu #define CLK_TOP_APLL1_D3 186 2268465baaeSWeiyi Lu #define CLK_TOP_APLL1_REF_SEL 187 2278465baaeSWeiyi Lu #define CLK_TOP_APLL2_REF_SEL 188 2288465baaeSWeiyi Lu #define CLK_TOP_NFI2X_EN 189 2298465baaeSWeiyi Lu #define CLK_TOP_NFIECC_EN 190 2308465baaeSWeiyi Lu #define CLK_TOP_NFI1X_CK_EN 191 2318465baaeSWeiyi Lu #define CLK_TOP_NR_CLK 192 232b7f1a721Sweiyi.lu@mediatek.com 233b7f1a721Sweiyi.lu@mediatek.com /* INFRACFG */ 234b7f1a721Sweiyi.lu@mediatek.com 235b7f1a721Sweiyi.lu@mediatek.com #define CLK_INFRA_DBGCLK 0 236b7f1a721Sweiyi.lu@mediatek.com #define CLK_INFRA_GCE 1 237b7f1a721Sweiyi.lu@mediatek.com #define CLK_INFRA_M4U 2 238b7f1a721Sweiyi.lu@mediatek.com #define CLK_INFRA_KP 3 239b7f1a721Sweiyi.lu@mediatek.com #define CLK_INFRA_AO_SPI0 4 240b7f1a721Sweiyi.lu@mediatek.com #define CLK_INFRA_AO_SPI1 5 241b7f1a721Sweiyi.lu@mediatek.com #define CLK_INFRA_AO_UART5 6 242b7f1a721Sweiyi.lu@mediatek.com #define CLK_INFRA_NR_CLK 7 243b7f1a721Sweiyi.lu@mediatek.com 244b7f1a721Sweiyi.lu@mediatek.com /* PERICFG */ 245b7f1a721Sweiyi.lu@mediatek.com 246b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_NFI 0 247b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_THERM 1 248b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM0 2 249b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM1 3 250b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM2 4 251b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM3 5 252b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM4 6 253b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM5 7 254b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM6 8 255b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM7 9 256b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PWM 10 257b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_AP_DMA 11 258b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC30_0 12 259b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC30_1 13 260b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC30_2 14 261b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC30_3 15 262b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_UART0 16 263b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_UART1 17 264b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_UART2 18 265b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_UART3 19 266b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_I2C0 20 267b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_I2C1 21 268b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_I2C2 22 269b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_I2C3 23 270b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_I2C4 24 271b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_AUXADC 25 272b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_SPI0 26 273b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_SPI 27 274b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_I2C5 28 275b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_SPI2 29 276b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_SPI3 30 277b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_SPI5 31 278b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_UART4 32 279b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_SFLASH 33 280b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_GMAC 34 281b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PCIE0 35 282b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_PCIE1 36 283b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_GMAC_PCLK 37 284b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC50_0_EN 38 285b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC30_1_EN 39 286b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC30_2_EN 40 287b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC30_3_EN 41 288b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC50_0_HCLK_EN 42 289b7f1a721Sweiyi.lu@mediatek.com #define CLK_PERI_MSDC50_3_HCLK_EN 43 2908465baaeSWeiyi Lu #define CLK_PERI_MSDC30_0_QTR_EN 44 2918465baaeSWeiyi Lu #define CLK_PERI_MSDC30_3_QTR_EN 45 2928465baaeSWeiyi Lu #define CLK_PERI_NR_CLK 46 293b7f1a721Sweiyi.lu@mediatek.com 294b7f1a721Sweiyi.lu@mediatek.com /* MCUCFG */ 295b7f1a721Sweiyi.lu@mediatek.com 296b7f1a721Sweiyi.lu@mediatek.com #define CLK_MCU_MP0_SEL 0 297b7f1a721Sweiyi.lu@mediatek.com #define CLK_MCU_MP2_SEL 1 298b7f1a721Sweiyi.lu@mediatek.com #define CLK_MCU_BUS_SEL 2 299b7f1a721Sweiyi.lu@mediatek.com #define CLK_MCU_NR_CLK 3 300b7f1a721Sweiyi.lu@mediatek.com 301b7f1a721Sweiyi.lu@mediatek.com /* MFGCFG */ 302b7f1a721Sweiyi.lu@mediatek.com 303b7f1a721Sweiyi.lu@mediatek.com #define CLK_MFG_BG3D 0 304b7f1a721Sweiyi.lu@mediatek.com #define CLK_MFG_NR_CLK 1 305b7f1a721Sweiyi.lu@mediatek.com 306b7f1a721Sweiyi.lu@mediatek.com /* MMSYS */ 307b7f1a721Sweiyi.lu@mediatek.com 308b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_SMI_COMMON 0 309b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_SMI_LARB0 1 310b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_CAM_MDP 2 311b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_RDMA0 3 312b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_RDMA1 4 313b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_RSZ0 5 314b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_RSZ1 6 315b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_RSZ2 7 316b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_TDSHP0 8 317b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_TDSHP1 9 318b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_CROP 10 319b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_WDMA 11 320b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_WROT0 12 321b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_WROT1 13 322b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_FAKE_ENG 14 323b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MUTEX_32K 15 324b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_OVL0 16 325b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_OVL1 17 326b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_RDMA0 18 327b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_RDMA1 19 328b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_RDMA2 20 329b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_WDMA0 21 330b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_WDMA1 22 331b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_COLOR0 23 332b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_COLOR1 24 333b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_AAL 25 334b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_GAMMA 26 335b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_UFOE 27 336b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_SPLIT0 28 337b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_OD 29 338b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_PWM0_MM 30 339b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_PWM0_26M 31 340b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_PWM1_MM 32 341b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_PWM1_26M 33 342b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DSI0_ENGINE 34 343b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DSI0_DIGITAL 35 344b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DSI1_ENGINE 36 345b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DSI1_DIGITAL 37 346b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DPI_PIXEL 38 347b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DPI_ENGINE 39 348b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DPI1_PIXEL 40 349b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DPI1_ENGINE 41 350b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_LVDS_PIXEL 42 351b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_LVDS_CTS 43 352b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_SMI_LARB4 44 353b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_SMI_COMMON1 45 354b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_SMI_LARB5 46 355b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_RDMA2 47 356b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_TDSHP2 48 357b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_OVL2 49 358b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_WDMA2 50 359b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_COLOR2 51 360b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_AAL1 52 361b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DISP_OD1 53 362b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_LVDS1_PIXEL 54 363b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_LVDS1_CTS 55 364b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_SMI_LARB7 56 365b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_RDMA3 57 366b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_MDP_WROT2 58 367b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DSI2 59 368b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DSI2_DIGITAL 60 369b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DSI3 61 370b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_DSI3_DIGITAL 62 371b7f1a721Sweiyi.lu@mediatek.com #define CLK_MM_NR_CLK 63 372b7f1a721Sweiyi.lu@mediatek.com 373b7f1a721Sweiyi.lu@mediatek.com /* IMGSYS */ 374b7f1a721Sweiyi.lu@mediatek.com 375b7f1a721Sweiyi.lu@mediatek.com #define CLK_IMG_SMI_LARB2 0 376b7f1a721Sweiyi.lu@mediatek.com #define CLK_IMG_SENINF_SCAM_EN 1 377b7f1a721Sweiyi.lu@mediatek.com #define CLK_IMG_SENINF_CAM_EN 2 378b7f1a721Sweiyi.lu@mediatek.com #define CLK_IMG_CAM_SV_EN 3 379b7f1a721Sweiyi.lu@mediatek.com #define CLK_IMG_CAM_SV1_EN 4 380b7f1a721Sweiyi.lu@mediatek.com #define CLK_IMG_CAM_SV2_EN 5 381b7f1a721Sweiyi.lu@mediatek.com #define CLK_IMG_NR_CLK 6 382b7f1a721Sweiyi.lu@mediatek.com 383b7f1a721Sweiyi.lu@mediatek.com /* BDPSYS */ 384b7f1a721Sweiyi.lu@mediatek.com 385b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_BRIDGE_B 0 386b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_BRIDGE_DRAM 1 387b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_LARB_DRAM 2 388b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_WR_CHANNEL_VDI_PXL 3 389b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_WR_CHANNEL_VDI_DRAM 4 390b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_WR_CHANNEL_VDI_B 5 391b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_MT_B 6 392b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_DISPFMT_27M 7 393b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_DISPFMT_27M_VDOUT 8 394b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_DISPFMT_27_74_74 9 395b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_DISPFMT_2FS 10 396b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_DISPFMT_2FS_2FS74_148 11 397b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_DISPFMT_B 12 398b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_VDO_DRAM 13 399b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_VDO_2FS 14 400b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_VDO_B 15 401b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_WR_CHANNEL_DI_PXL 16 402b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_WR_CHANNEL_DI_DRAM 17 403b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_WR_CHANNEL_DI_B 18 404b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_NR_AGENT 19 405b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_NR_DRAM 20 406b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_NR_B 21 407b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_BRIDGE_RT_B 22 408b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_BRIDGE_RT_DRAM 23 409b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_LARB_RT_DRAM 24 410b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_TVD_TDC 25 411b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_TVD_54 26 412b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_TVD_CBUS 27 413b7f1a721Sweiyi.lu@mediatek.com #define CLK_BDP_NR_CLK 28 414b7f1a721Sweiyi.lu@mediatek.com 415b7f1a721Sweiyi.lu@mediatek.com /* VDECSYS */ 416b7f1a721Sweiyi.lu@mediatek.com 417b7f1a721Sweiyi.lu@mediatek.com #define CLK_VDEC_CKEN 0 418b7f1a721Sweiyi.lu@mediatek.com #define CLK_VDEC_LARB1_CKEN 1 419b7f1a721Sweiyi.lu@mediatek.com #define CLK_VDEC_IMGRZ_CKEN 2 420b7f1a721Sweiyi.lu@mediatek.com #define CLK_VDEC_NR_CLK 3 421b7f1a721Sweiyi.lu@mediatek.com 422b7f1a721Sweiyi.lu@mediatek.com /* VENCSYS */ 423b7f1a721Sweiyi.lu@mediatek.com 424b7f1a721Sweiyi.lu@mediatek.com #define CLK_VENC_SMI_COMMON_CON 0 425b7f1a721Sweiyi.lu@mediatek.com #define CLK_VENC_VENC 1 426b7f1a721Sweiyi.lu@mediatek.com #define CLK_VENC_SMI_LARB6 2 427b7f1a721Sweiyi.lu@mediatek.com #define CLK_VENC_NR_CLK 3 428b7f1a721Sweiyi.lu@mediatek.com 429b7f1a721Sweiyi.lu@mediatek.com /* JPGDECSYS */ 430b7f1a721Sweiyi.lu@mediatek.com 431b7f1a721Sweiyi.lu@mediatek.com #define CLK_JPGDEC_JPGDEC1 0 432b7f1a721Sweiyi.lu@mediatek.com #define CLK_JPGDEC_JPGDEC 1 433b7f1a721Sweiyi.lu@mediatek.com #define CLK_JPGDEC_NR_CLK 2 434b7f1a721Sweiyi.lu@mediatek.com 435b7f1a721Sweiyi.lu@mediatek.com #endif /* _DT_BINDINGS_CLK_MT2712_H */ 436